High-performance designs with CMOS analog standard cells

Pletersek, T.; Trontelj, Janez; Trontelj, L.; Jones, Ian W.; Shenton, G.

doi:10.1109/jssc.1986.1052506

Cited by 27 publications

(6 citation statements)

References 2 publications

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“…(2) Yael R sub = (R x _ acl + RX_Sli)//(Ry_aCI + R y _ Sli ) (1) where R X _ ael and R Y _ ael are resistances under the active region, R Y _ Sli and R y _ sti are the resistances under shallow trench isolation (STI) regions in the x and Y directions, which can be calculated for both directions as in equation (2) and (3).…”

Section: Passive Sub-circuit Cellsmentioning

confidence: 99%

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Cell-based high-frequency IC design in scaled CMOS

Yue

Shin

2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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This paper presents a cell-based modeling and design platform for high-frequency analog ICs to shorten design cycle time and to minimize the risk for mask re-spin. Based on a pre-characterized analog sub-circuit cell library, which contains not only active devices and passive components but also routing interconnects. This methodology systematically alleviates modeling inaccuracy at high frequencies due to the difference in the layout between device test structures and actual circuit implementation. By exploiting the modularity in analog circuits at the sub-circuit level, the proposed design platform achieves a balance between design flexibility and modeling accuracy compared. The macro modeling techniques the sub-circuit cells will be described along with measurement results from a characterization test chip.

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Section: Passive Sub-circuit Cellsmentioning

confidence: 99%

“…Standard-ceIl-based analog design was first proposed and attempted in a 3-J.lm CMOS process nearly two decades ago [1] [2]. The feasibility of such analog design methodology is hampered by the performance penalty, design flexibility and area overhead.…”

Section: Introductionmentioning

confidence: 99%

Cell-based high-frequency IC design in scaled CMOS

Yue

Shin

2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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“…The cell-based analog layout methodology was first attempted in a 3-μm CMOS process nearly two decades ago [1] [2]. More recently, a RF cell-based modeling platform for parameterized sub-circuit cells layout was proposed based on a 0.13-μm CMOS process [3].…”

Section: Introductionmentioning

confidence: 99%

A performance study of layout and V<inf>t</inf> options for low noise amplifier design in 65-nm CMOS

Pan

Yeh

Jou

et al. 2012

2012 IEEE Radio Frequency Integrated Circuits Symposium

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This paper studies the trade-off between different cell-based layout styles and V t options using a set of 5-GHz differential cascode LNAs. The test chip is fabricated in 65-nm CMOS process. The impact of merged diffusion area at the cascode node, the effect of gate contact style as well as the usage of normal V t versus low V t are presented. Our measurement results show that using individual device layout with separated diffusion area, low V t and double-sided gate contact provides better gain and noise performance. Specifically, the power gain and noise figure (NF) are improved by 1.5 dB and 0.3 dB, respectively, under the same bias current and power consumption. On the other hand, using normal V t devices with merged diffusion area achieves significantly better linearity with about 4-dBm increase in IIP3. Based on these findings, recommended layout and V t usage guidelines for RF amplifier design in 65-nm technology are proposed.Index Terms -device characterization, low noise amplifier, cell-based layout, V t options, noise figure, power gain, matching.

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“…Standard-cell-based analog design was first proposed and attempted in a 3-Pm CMOS process nearly two decades ago [1] [2]. The feasibility of such analog design methodology is hampered by the performance penalty, design flexibility and area overhead.…”

Section: Introductionmentioning

confidence: 99%

Cell-Based High-Frequency IC Design in Scaled CMOS

Yue

Shin

2007

2007 IEEE International Workshop on Radio-Frequency Integration Technology

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This paper presents a cell-based modeling and design platform for high-frequency analog ICs to shorten design cycle time and to minimize the risk for mask re-spin. Based on a pre-characterized analog subcircuit cell library, which contains not only active devices and passive components but also routing interconnects. This methodology systematically alleviates modeling inaccuracy at high frequencies due to the difference in the layout between device test structures and actual circuit implementation. By exploiting the modularity in analog circuits at the sub-circuit level, the proposed design platform achieves a balance between design flexibility and modeling accuracy compared. The macro modeling techniques the sub-circuit cells will be described along with measurement results from a characterization test chip. The design and measured results of an UWB LNA utilizing the cell library will be presented.

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High-performance designs with CMOS analog standard cells

Cited by 27 publications

References 2 publications

Cell-based high-frequency IC design in scaled CMOS

Cell-based high-frequency IC design in scaled CMOS

A performance study of layout and V<inf>t</inf> options for low noise amplifier design in 65-nm CMOS

Cell-Based High-Frequency IC Design in Scaled CMOS

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