High performance and low power FIR filter design based on sharing multiplication

Park, Jongsun; Jeong, Won-Ki; Choo, Hunsoo; Mahmoodi, Hamid; Wang, Yongtao; Roy, Kaushik

doi:10.1145/566408.566485

Cited by 16 publications

(7 citation statements)

References 12 publications

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“…A number of proposed techniques have used alphabets to pre-compute multiples of the multiplicand to be selected based on multiplier bits and shared this pre-computer for all multiplications in the TDF FIR filter [103][104][105][106][107][108][109]. However, this approach is a special case of high-radix multiplication when the radix is 16.…”

Section: Reduction In Multiplier Complexitymentioning

confidence: 99%

“…For example, in [103][104][105][106][107][108] the authors present a computation sharing multiplier where the bank of pre-computers generate odd multiples between 1X and 15X, which is an example of a radix-16 standard high-radix multiplier with other multiples being non-trivial and generated using just shifts. Also in [213] authors propose a common subexpression elimination where the multiples produced are again a case of radix-8 standard high-radix multiplication.…”

Section: Booth Algorithm -Original and Modifiedmentioning

confidence: 99%

“…The parallel summation is primarily a problem of multi-operand addition which is solved either using (m, 2) compressors, array accumulation and tree accumulation [123]. Within these broad schemes, a number of different techniques have been proposed like Wallace tree adder array using carry-save adders [103,104,107,214], logarithmic carry-select adder [105] and carry-select adder using dual transition skewed logic (DTSL) [106,108].…”

Section: B Partial Product Summationmentioning

confidence: 99%

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Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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Section: Reduction In Multiplier Complexitymentioning

confidence: 99%

Section: Booth Algorithm -Original and Modifiedmentioning

confidence: 99%

Section: B Partial Product Summationmentioning

confidence: 99%

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Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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“…Urdhava Tiryagbhyam is Sanskrit word which signifies "Vertically and across" [8,9]. The increase depends on a calculation called Urdhava Tiryagbhyam (Vertical and Crosswise) of old Indian Vedic Mathematics.…”

Section: Urdhava-tiryagbhyammentioning

confidence: 99%

Fir Filter Design With Speed Multiplier

2016

IJAERD

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“…The computation sharing approach is effective to reduce surplus component involved for filtering by recognizing the familiar computations. [5] proposed FIR filter implementation with resource allocation algorithm for the higher performance and comparable power consumption with pre-emptive tasks with FIR filters based on the carry-save-array multiplier (CSAM) and Wallace tree multiplier (WTM), also used in DSP to speed up the operations and adaptive filter applications. [6] has developed a FIR filter using UrdhavaTiryagbhyam algorithm to improve the performance of the system.…”

Section: Introductionmentioning

confidence: 99%

High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier

Jayakumar¹,

Sumathi²

2016

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In this, today's world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology, many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed-up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay; area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesized with Xilinx.

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High performance and low power FIR filter design based on sharing multiplication

Cited by 16 publications

References 12 publications

Techniques for Efficient Implementation of FIR and Particle Filtering

Techniques for Efficient Implementation of FIR and Particle Filtering

Fir Filter Design With Speed Multiplier

High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier

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