High performance and cost effective memory architecture for an HDTV decoder LSI

Takizawa, T.; Tajime, Junji; Harasaki, H.

doi:10.1109/icassp.1999.758315

Cited by 15 publications

(11 citation statements)

References 5 publications

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“…Figure 3 (a) shows the conventional 1-D DPCM prediction structure used in [1,5,6] and the number of bits allocated to luminance pixels (a base pixel and prediction error pixels). Here, a 1-D DPCM block consists of eight consecutive pixels.…”

Section: Degradation Mechanism In H264 Decodermentioning

confidence: 99%

“…While products are able to offer picture-in-picture and watch-and-record functions, these functions require a decoder having either double or more memory bandwidth, which means consumers have to pay more or give up the functions. Memory compression methods for reducing memory bandwidth have been proposed for MPEG-2 decoders [1][2][3][4][5][6][7]. Although these methods generate distortion, image quality degradation due to that distortion is negligible.…”

Section: Introductionmentioning

confidence: 99%

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A Memory Compression Method for Avoiding Perceivable Distortion Due to Intra-Prediction in H.264 Decoders

Tajime

Miyamoto

2007

2007 Digest of Technical Papers International Conference on Consumer Electronics

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This paper analyzes the video-quality degradation mechanism in an H.264 decoder with memory compression and proposes a new DPCM memory compression method which avoids that degradation. When memory compression methods used in MPEG-2 decoders are applied to H.264 decoders, heavy degradation sometimes occurs because H.264 employs directional spatial prediction in intra-coding. The proposed method avoids such degradation by deploying DPCM base points to intra reference pixels in order to protect them from compression distortion. Simulation results show that the proposed method significantly improves video-quality, in the best case by 7.51dB in PSNR, over that of conventional methods, and subjective quality is also improved.

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Section: Degradation Mechanism In H264 Decodermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Memory Compression Method for Avoiding Perceivable Distortion Due to Intra-Prediction in H.264 Decoders

Tajime

Miyamoto

2007

2007 Digest of Technical Papers International Conference on Consumer Electronics

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“…SDRAM architecture is introduced in [4][7] [8]. Its bandwidth consumption consists of CAS (Column Access Strobe) cycles and overhead].…”

Section: Memory Bandwidth Requirementsmentioning

confidence: 99%

“…The gap between them causes memory bandwidth a bottleneck in overall system performance. Efficient memory controller design is a key technique in video decoder designs [3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

“…Methods have been worked out to avoid bank conflict, the major overhead of SDRAM. Macroblock-based mapping [4][5] [7] can substantially reduce bank conflict overhead within one macroblock(MB); memory access scheduling [5][6] reorders memory accesses to insert nonconflicted accesses between conflicted ones, and memory mode prediction [8] reduces conflict overhead by adaptively using auto-precharge. But H.264 requires much more memory bandwidth than MPEG2, because of long tap interpolation filter, dispersive reference blocks and additional mass data that need to store off-chip.…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder

Zhang

Gao

et al. 2006

2006 IEEE International Conference on Multimedia and Expo

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This paper proposes an efficient reference frame storage scheme for HDTV VLSI decoder to reduce external memory bandwidth requirement. The proposed scheme consists of the pixel duplication mechanism and the L-C (luma-chroma) correlated mapping method. Pixel duplication completely eliminates the possibility of an access crossing word boundary and therefore substantially increases the memory bandwidth efficiency. L-C correlated mapping exploits address relationships between the luma and chroma reference pixels and largely reduces bank conflict overhead of memory accesses. The two mechanisms combined together efficiently improve the bandwidth usage: up to 47% bandwidth in worst case is saved compared with the previous schemes, and 25% in average case.

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Auxiliary stream for optimizing memory access of video decoders

Liu

Chen

et al. 2014

Sci. China Inf. Sci.

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Due to the ever increasing resolution and frame rate of mainstream video sequences, memory access has become the main performance bottleneck of video decoding. To reduce the required off-chip memory, many decoders employ on-chip cache. However, they cannot distinguish whether a data block is reusable due to the lack of the information of undecoded Macro Blocks (MBs), thus often evicting reusable data from the cache and preserving non-reusable data in the cache, which will lead to a waste of off-chip memory bandwidth. In this paper, we manage to make full use of cache from a novel perspective, i.e., auxiliary bitstream. Concretely speaking, since the memory access behavior of video decoding is determined in video encoding, the encoder can pack the memory access behaviors of video decoding as auxiliary bitstream, which can inform the decoder whether a data block will be reused by future MBs. Hence, such an auxiliary stream can enable optimal management of cache. To effectively reduce the size of auxiliary bitstream, we propose an Auxiliary Prior Information Coding (APIC) method complying with the current video standards. For future video standards, we introduce a Super Block scan Order (SBO) for MB organization to further reduce the bitrate overhead of auxiliary bitstream. The above ideas are evaluated on a number of representative video sequences. The additional prior information can reduce the required off-chip memory bandwidth for motion compensation by over 35% (for a 60 kB cache), while only causing less than 2.3% bitrate increase for high definition (HD) videos.

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High performance and cost effective memory architecture for an HDTV decoder LSI

Cited by 15 publications

References 5 publications

A Memory Compression Method for Avoiding Perceivable Distortion Due to Intra-Prediction in H.264 Decoders

A Memory Compression Method for Avoiding Perceivable Distortion Due to Intra-Prediction in H.264 Decoders

An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder

Auxiliary stream for optimizing memory access of video decoders

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