High Mobility High-Ge-Content SiGe PMOSFETs Using Al2O3/HfO2 Stacks With &lt;italic&gt;In-Situ&lt;/italic&gt; O3 Treatment

Ando, Takashi; Hashemi, Pouya; Bruley, J.; Rozen, John; Ogawa, Y.; Koswatta, Siyuranga O.; Chan, K.; Cartier, E.; Mo, R.; Narayanan, V.

doi:10.1109/led.2017.2654485

Cited by 40 publications

(29 citation statements)

References 7 publications

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“…But the small dielectric thickness and interface quality issues of high κ dielectrics will cause serious reliability problems. Thus, a stack gate dielectric of 0.5 nm of Al 2 O 3 and 2.0 nm of HfO 2 is set to guarantee a good interface quality [27][28][29], which can significantly reduce the leakage current and improve the reliability of gate dielectric. The source electrode is located on the top of the fin structure.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

et al. 2020

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In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

et al. 2020

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“…On the contrary, if the quantum confinement and strain splitting are subtractive, the total mobility will not be as high as the addition situation. When uniaxial tensile stress along [110] orientation in the (001) plane ([110] /(001) for short) Si is applied, stress makes the Δ 2 valleys further decline according to (9), so the quantum confinement and strain splitting are additive.…”

Section: (001) Strained Si Electron Mobilitymentioning

confidence: 99%

“…They are highly accurate but too complicated and time‐consuming, and are hard to embed in the device simulation software so that cannot be used in the simulation of the actual circuit. The effective mobility can also be assessed by split

C - V

technique [9, 10] and Y‐function method [11, 12]. They are similar with empirical and semi‐empirical models, which are simple and easy to use, but the parameters need to be extracted from the actual device, therefore, their universality are often questioned.…”

Section: Introductionmentioning

confidence: 99%

Analytical model for uniaxial strained Si inversion layer electron effective mobility

Wang

2019

IET Circuits, Devices & Systems

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The electron effective mobility analytical model without empirical parameters is investigated for uniaxial strained Si inversion layer, which can be conveniently applied by device and circuit designers. By one-dimensional inverse transform for the three-dimensional (3D) scattering matrix element along the vertical channel direction, three scattering (coulomb scattering, acoustic phonon scattering and intervalley scattering) rate models are researched. Then, the surface roughness scattering rate is taken into account to calculate the 2D inversion layer electron mobility. Based on the models, the simulations have been carried out by Matlab. The simulation results are in accord with the reference data, and the saturation phenomenon is brought to light.

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“…For instance, it was reported that for pure Ge substrates, increasing the barrier Al 2 O 3 thickness (1 to 1.5nm) prior to post-oxidation reduces the GeO x IL thickness (from 1.2 to 0.23 nm) and unexpectedly increases D it (~5×) 20 . For SiGe substrates, it was shown that post ALD oxidation on low Ge content SiGe (30% to 50%) forms a highly defective SiGeO x interface, and the thickness of the IL decreases for higher Ge composition SiGe (Si 0.69 Ge 0.31 to Si 0.5 Ge 0.95 ) due to suppression of SiO x in the IL 21 . However, DFT and experimental studies shown that formation of an SiO x interface between SiGe and oxide results in an extremely low interfacial defect density on low Ge content SiGe 18 .…”

Section: Introductionmentioning

confidence: 99%

Understanding the Mechanism of Electronic Defect Suppression Enabled by Nonidealities in Atomic Layer Deposition

et al. 2019

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Silicon germanium (SiGe) is a multi-functional material considered for quantum computing, neuromorphic devices and CMOS transistors. However, implementation of SiGe in nano-scale electronic devices necessitates suppression of surface states dominating on electronic properties. The absence of a stable and passive surface oxide for SiGe results formation of charge traps at the SiGe -oxide interface induced by GeO x . In an ideal ALD process in which oxide is grown layer-by-layer, the GeO x formation should be prevented with selective surface oxidation (i.e. formation of an SiO x interface) by controlling oxidant dose in first few ALD cycles of the oxide deposition on SiGe. However, in a real ALD process, the interface evolves during entire ALD oxide deposition due to diffusion of reactant species through the gate oxide. In this work, this diffusion process in non-ideal ALD is investigated and exploited: the diffusion through the oxide during ALD is utilized to passivate the interfacial defects by employing ozone as a secondary oxidant. Periodic ozone exposure during gate oxide ALD on SiGe is shown to reduce the integrated trap density (D it ) across the band gap by nearly an order of magnitude in Al 2 O 3 (< 6×10 10 cm -2 ) and in HfO 2 (< 3.9×10 11 cm -2 ) by forming a SiO x rich interface on SiGe. Depletion of Ge from the interfacial layer (IL) by enhancement of volatile GeO x formation and consequent desorption from the SiGe with ozone insertion during ALD growth process is confirmed by electron energy loss spectroscopy (STEM-EELS) and hypothesized to be the mechanism for reduction of the interfacial defects. In this work, the nanoscale mechanism for defect suppression at SiGe oxide interface is demonstrated which is engineering of diffusion species in ALD process due to facile diffusion of reactant species in non-ideal ALD.

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High Mobility High-Ge-Content SiGe PMOSFETs Using Al₂O₃/HfO₂ Stacks With <italic>In-Situ</italic> O₃ Treatment

Cited by 40 publications

References 7 publications

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

Analytical model for uniaxial strained Si inversion layer electron effective mobility

Understanding the Mechanism of Electronic Defect Suppression Enabled by Nonidealities in Atomic Layer Deposition

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