High-Level Test Synthesis

Ravi, S.; Joseph, Mathai

doi:10.1145/2627754

Cited by 7 publications

(1 citation statement)

References 41 publications

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“…At the beginning of the traditional system on chip (SoC) hardware design flow, the behavioral description of the design systems needs to be written using the hardware description language [7], which is the register transfer level (RTL) of abstraction. Recently, due to the increasing popularity of hardware accelerators, the abstraction level is rising from RTL to the algorithmic level, which is described using high-level languages such as C, C++, SystemC, or Simulink and then followed by an automated high-level synthesis (HLS) flow to synthesize these descriptions to generate RTL [23][24][25][26]. These multiple processes of system description allow designers to evaluate multiple alternatives, which is known as design space exploration (DSE) [27,28].…”

Section: Introductionmentioning

confidence: 99%

Feasibility Prediction for Rapid IC Design Space Exploration

Islam

2022

Electronics

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The DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools, and even many days to complete a design implementation. However, at the end of this process, some designs could not meet the design constraints and become unroutable, creating a vicious circuit design cycle. As a result, designers have to re-run the whole process after design modification. This research applied a machine learning approach to automatically identify design constraints and design rule checking (DRC) violation issues and help the designer identify design constraints with optimal DRCs before the long detailed routing process through iterative greedy search. The proposed algorithm achieved up to 99.99% design constraint prediction accuracy and reduced 98.4% DRC violations with only a 6.9% area penalty.

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Section: Introductionmentioning

confidence: 99%

Feasibility Prediction for Rapid IC Design Space Exploration

Islam

2022

Electronics

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LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

Qamar

Muslim

Iqbal

et al. 2017

Microprocessors and Microsystems

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The abstraction level for digital designs is rising from Register Transfer Level (RTL) to algorithmic untimed or transaction-based, followed by an automated high level synthesis (HLS) flow. However, it is still a significant challenge for chip architects and designers to describe low-power design decisions at the system level. Nowadays, low power design techniques for digital blocks are applied at RTL and there exists no commercial tool or methodology that can automatically derive the power intent from the system level description. The process requires considerable amount of human intervention and various lower-level details that are needed to implement low power schemes at RTL. This research aims to integrate low power techniques, specifically Power Shut-Off (PSO), within a model based hardware flow and to derive an automated Low Power-High Level Synthesis (LP-HLS) methodology. The methodology aims at minimizing the design effort for low power design by deriving low-level power intent automatically for model-based designs, while using high level synthesis to achieve a broad set of target system implementations. All the information that is needed to implement low power techniques is automatically derived from the systemlevel design using a set of pragmas and a directives file. To illustrate the methodology, three model designs, ranging from simple designs to medium complexity hardware accelerators, are considered. Finally, the power saving results for the design scenarios validate the effectiveness of our LP-HLS methodology. • Hardware~Best practices for EDA • Hardware~Software tools for EDA • Hardware~Hardware description languages and compilation • Hardware~Modeling and parameter extractionAdditional Key Words and Phrases: Hardware accelerators, HLS, RTL, design space exploration, common power format, low power designs, design automation.

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