Feasibility Prediction for Rapid IC Design Space Exploration

Islam, Riadul

doi:10.3390/electronics11071161

Cited by 4 publications

(2 citation statements)

References 38 publications

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“…1. As a result, early stage routing prediction attracts great attention from the research community [2], [7], [9], [10]. The existing synthesis tools use only global routing congestion report for routability prediction, however, disputed by the research community on the effectiveness of this method [2], [10].…”

Section: A Motivationmentioning

confidence: 99%

Early Stage DRC Prediction Using Ensemble Machine Learning Algorithms

Islam

2022

IEEE Can. J. Electr. Comput. Eng.

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Section: A Motivationmentioning

confidence: 99%

Early Stage DRC Prediction Using Ensemble Machine Learning Algorithms

Islam

2022

IEEE Can. J. Electr. Comput. Eng.

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“…are using AI/ ML to improve the productivity of their tools. Furthermore, researchers play a crucial role in the development of AI/ML-based EDA tools [ 33 , 34 , 35 , 36 , 37 , 38 ]. However, a generic end-to-end tool for ANN-to-SNN conversion and SNN-to-hardware layout is yet to be developed.…”

Section: Introductionmentioning

confidence: 99%

Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks

Islam,

Majurski,

Kwon

et al. 2024

Sensors

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Organizations managing high-performance computing systems face a multitude of challenges, including overarching concerns such as overall energy consumption, microprocessor clock frequency limitations, and the escalating costs associated with chip production. Evidently, processor speeds have plateaued over the last decade, persisting within the range of 2 GHz to 5 GHz. Scholars assert that brain-inspired computing holds substantial promise for mitigating these challenges. The spiking neural network (SNN) particularly stands out for its commendable power efficiency when juxtaposed with conventional design paradigms. Nevertheless, our scrutiny has brought to light several pivotal challenges impeding the seamless implementation of large-scale neural networks (NNs) on silicon. These challenges encompass the absence of automated tools, the need for multifaceted domain expertise, and the inadequacy of existing algorithms to efficiently partition and place extensive SNN computations onto hardware infrastructure. In this paper, we posit the development of an automated tool flow capable of transmuting any NN into an SNN. This undertaking involves the creation of a novel graph-partitioning algorithm designed to strategically place SNNs on a network-on-chip (NoC), thereby paving the way for future energy-efficient and high-performance computing paradigms. The presented methodology showcases its effectiveness by successfully transforming ANN architectures into SNNs with a marginal average error penalty of merely 2.65%. The proposed graph-partitioning algorithm enables a 14.22% decrease in inter-synaptic communication and an 87.58% reduction in intra-synaptic communication, on average, underscoring the effectiveness of the proposed algorithm in optimizing NN communication pathways. Compared to a baseline graph-partitioning algorithm, the proposed approach exhibits an average decrease of 79.74% in latency and a 14.67% reduction in energy consumption. Using existing NoC tools, the energy-latency product of SNN architectures is, on average, 82.71% lower than that of the baseline architectures.

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Reconfigurable CAN Intrusion Detection and Response System

Saini,

Islam

2024

Electronics

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The controller area network (CAN) remains the de facto standard for intra-vehicular communication. CAN enables reliable communication between various microcontrollers and vehicle devices without a central computer, which is essential for sustainable transportation systems. However, it poses some serious security threats due to the nature of communication. According to caranddriver.com, there were at least 150 automotive cybersecurity incidents in 2019, a 94% year-over-year increase since 2016, according to a report from Upstream Security. To safeguard vehicles from such attacks, securing CAN communication, which is the most relied-on in-vehicle network (IVN), should be configured with modifications. In this paper, we developed a configurable CAN communication protocol to secure CAN with a hardware prototype for rapidly prototyping attacks, intrusion detection systems, and response systems. We used a field programmable gate array (FPGA) to prototype CAN to improve reconfigurability. This project focuses on attack detection and response in the case of bus-off attacks. This paper introduces two main modules: the multiple generic errors module with the introduction of the error state machine (MGEESM) module and the bus-off attack detection (BOAD) module for a frame size of 111 bits (BOAD111), based on the CAN protocol presenting the introduction of form error, CRC error, and bit error. Our results show that, in the scenario with the transmit error counter (TEC) value 127 for switching between the error-passive state and bus-off state, the detection times for form error, CRC error, and bit error introduced in the MGEESM module are 3.610 ms, 3.550 ms, and 3.280 ms, respectively, with the introduction of error in consecutive frames. The detection time for BOAD111 module in the same scenario is 3.247 ms.

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Feasibility Prediction for Rapid IC Design Space Exploration

Cited by 4 publications

References 38 publications

Early Stage DRC Prediction Using Ensemble Machine Learning Algorithms

Early Stage DRC Prediction Using Ensemble Machine Learning Algorithms

Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks

Reconfigurable CAN Intrusion Detection and Response System

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