High-level synthesis with reconfigurable datapath components

Economakos,

doi:10.1109/ipdps.2006.1639477

Cited by 3 publications

(3 citation statements)

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“…A heuristic scheduling algorithm, which utilizes reconfigurable datapath components, has been presented in [19]. In this case, the resulting schedule is shortened so that the gain in execution clock cycles compensates the configuration time overhead.…”

Section: Related Workmentioning

confidence: 99%

Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

2010

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High latencies in FPGA reconfiguration are known as a major overhead in run-time reconfigurable systems. This overhead can be reduced by merging multiple data flow graphs representing different kernels of the original program into a single (merged) datapath that will be configured less often compared to the separate datapaths scenario. However, the additional hardware introduced by this technique increases the kernels execution time. In this paper, we present a novel datapath merging technique that reduces both the configuration and execution times of kernels mapped on the reconfigurable fabric. Experimental results show up to 13% reduction in the configuration and execution times of kernels from media-bench workloads, compared to previous art on datapath merging. When compared to conventional high-level synthesis algorithms, our proposal reduces kernels configuration and execution times by up to 48%.

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Section: Related Workmentioning

confidence: 99%

Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

2010

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“…Reconfigurable computing for HLS is reported in [1] and [5]. In [1] the problem of register binding of the RTL description is considered and a technique to utilize on-chip embedded memory (found in modern FPGA devices) for this task is proposed.…”

Section: Related Researchmentioning

confidence: 99%

“…In [1] the problem of register binding of the RTL description is considered and a technique to utilize on-chip embedded memory (found in modern FPGA devices) for this task is proposed. In [5] a scheduling heuristic is proposed, offering shorter schedules but requiring many and frequent PRTRs, which may impose impractical overhead when applied to traditional reconfigurable devices. In fact, the solution of [5] is aimed toward future architectures with very small reconfiguration time.…”

Section: Related Researchmentioning

confidence: 99%

A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis

Economakos

Xydis

2008

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools

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Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. In this paper, a special type of course grain reconfigurable RTL components, called morphable multipliers, are used as parts of the implementation architecture, during a high-level synthesis scheduling postprocessing stage. With this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show a maximum performance gain of 60% with an average 25% area gain.

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