A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis

Abstract

Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. In this paper, a special type of course grain reconfigurable RTL components, called morphable multipliers, are used as parts of the implementation architecture, during a high-level synthesis scheduling postprocessing stage. With this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show a maximum performance gain of 60% with an average 25% area gain.