High-Level Abstractions and Modular Debugging for FPGA Design Validation

Abstract

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide visibility and control of the different stages of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated directly by the software reference model. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.

Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications

“…Their work, however, does not support most of the compiler optimizations performed during the HLS, and the use of SignalTap causes a high memory usage for the trace buffers, as reported also in Reference [33]. Iskander et al [27] propose an approach composed by two parts: a High-level Validation and Low level Debug. For the High-level Validation they run the golden reference software on a softcore on the FPGA, saving the results and comparing them with the results obtained from the accelerators.…”

Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis

“…The golden reference and the hardware signature are compared at the end of the execution and bugs are automatically detected. Iskander et al [19] propose a different hybrid approach composed by two parts: a High-Level Validation and Low Level Debug. For the High-Level Validation they run the golden reference software on a softcore on the FPGA, saving the results and comparing them with the results obtained from the accelerators.…”

Improving the productivity of high-level synthesis by advancing reuseability and verifiability

“…To directly affect productivity of source-level debugging, several academic and commercial HLS tools have added verification and debug support to their tool flows [47,34,58,59,43,45,44,46,95]. These verification techniques include detecting HW/SW execution discrepancy (simulation-based or on-board execution-based), developing software-like debug environments, and synthesizing C assertions to hardware.…”

“…Several commercial [34, 58,59] and academic tools [47] couple hardware execution with a software reference model to compare outputs from both executions at runtime. However, they typically compare output streams at the interface level and thus lack detailed internal behavior to diagnose the cause for mismatched execution.…”

“…Together, we identify that efficiency in use of reusable IP blocks and the verification and debug process are two critical factors affecting productivity of HLS-based design flows. Various research efforts attempt to address aspects in productivity, including performance monitoring and prediction [36,37] to reduce design iterations by improving early identification of bottlenecks, HW/SW co-design [38,39,40] to improve early mapping decisions, integration of reusable components [41,42], and verification [43,44,45,46,47] for better debugging efficiency.…”