2017 IEEE International Electron Devices Meeting (IEDM) 2017
DOI: 10.1109/iedm.2017.8268438
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High-k metal gate fundamental learning and multi-V<inf>t</inf> options for stacked nanosheet gate-all-around transistor

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Cited by 33 publications
(17 citation statements)
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“…With CMOS technology development, the reliability issues of advanced CMOS technology are becoming more challenging and complicated due to the novel material, novel process and novel device structure, e.g., Ge/GeSi channels, atom layer etching (ALE) technology, nanowires and nanosheets, etc., specially for 5 nm node and beyond [ 287 , 288 , 289 , 290 ]. Next, the transistor reliability challenge of advanced CMOS will be discussed.…”
Section: Advanced Devices Reliablitymentioning
confidence: 99%
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“…With CMOS technology development, the reliability issues of advanced CMOS technology are becoming more challenging and complicated due to the novel material, novel process and novel device structure, e.g., Ge/GeSi channels, atom layer etching (ALE) technology, nanowires and nanosheets, etc., specially for 5 nm node and beyond [ 287 , 288 , 289 , 290 ]. Next, the transistor reliability challenge of advanced CMOS will be discussed.…”
Section: Advanced Devices Reliablitymentioning
confidence: 99%
“…Recently, novel devices such as FinFETs, nanowires, and nanosheets, as the best candidates for advanced CMOS technology, have been widely studied [ 287 , 288 ]. In order to meet the better performance of novel devices, advanced processes e.g., filling and etching in 3D device structure, are proposed [ 291 , 292 ].…”
Section: Advanced Devices Reliablitymentioning
confidence: 99%
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“…In advanced CMOS technology, in order to reduce the influence of the thermal budget on junction and channel quality, introducing the novel materials and processes are necessary in gate engineering. Therefore, the dipole formation in the gate stack is widely applied in the Replacement Metal Gate (RMG) process [168,169,170,171,172,173]. Usually, Lanthanum (La) and Aluminum (Al) are used to tune threshold voltage for NFET and PFET due to the different dipole polarity [168,169,170,171].…”
Section: Reliabilitymentioning
confidence: 99%
“…This includes metal deposition (La or Al) and annealing treatment with or without a capping layer [168]. It has been reported that La induced dipole effectively, which makes V T decrease and positive bias temperature instability (PBTI) improve, but NBTI is worsened [168,169]. Meanwhile, the Al induced dipole increases V T and BTI becomes worse as well.…”
Section: Reliabilitymentioning
confidence: 99%