High Hole-Mobility Strained-$\hbox{Ge/Si}_{0.6} \hbox{Ge}_{0.4}$ P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness

Hashemi, Pouya; Hoyt, Judy L.

doi:10.1109/led.2011.2176913

Cited by 39 publications

(35 citation statements)

References 8 publications

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“…the energy bands was taken into account. The sidewall EOT (~1 nm) is smaller than the top EOT (~1.5 nm) due to differences in the GeOx and SiOx interface layers (2,10). A large fraction of the carriers are located near the sidewalls because of this and the s-Si/s-Ge valence band offset.…”

Section: Discussionmentioning

confidence: 98%

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High mobility high-κ-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs

Chern¹,

Hashemi

Teherani³

et al. 2012

2012 International Electron Devices Meeting

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We demonstrate for the first time, asymmetrically strained Ge, high-κ/metal gate nanowire (NW) trigate p-MOSFETs with record hole mobility of 1490 cm 2 /Vs. This mobility is 2× above on-chip, biaxially strained Ge planar FETs and ~15×above Si universal mobility. The fabrication approach features: (1) a new strained Si/strained Ge/HfO 2 NW channel materials stack, with HfO 2 dielectric at the bottom which acts as an excellent etch stop for top-down NW formation, and also unpins the back Ge-dielectric interface, (2) large compressive biaxial strain (~2.5%) that is built into the channel material prior to layer transfer, and (3) lateral strain relaxation by nanoscale patterning of the channel. The resulting asymmetric strain distribution dramatically reduces the conductivity effective mass. 6×6 k.p quantum mechanical simulations predict an increase in the Ge NW average inverse effective mass by a factor of 1.6 relative to planar biaxially strained Ge, consistent with the measured 2× mobility enhancement.

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Section: Discussionmentioning

confidence: 98%

“…Extremely high hole mobility (~1000 cm 2 /Vs) has been reported in planar high-κ/metal gate MOSFETs with Ge channels under biaxial compression (1,2).…”

Section: Introductionmentioning

confidence: 99%

High mobility high-κ-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs

Chern¹,

Hashemi

Teherani³

et al. 2012

2012 International Electron Devices Meeting

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“…In our laboratory, significant work has been conducted on the deposition of high quality Al 2 O 3 on Si and strained Si/strained Ge heterostructures with minimal density of interface traps (D it ) and mobile oxide charge that causes hysteresis. [30][31][32][33] In the present work, the D it of a Si control wafer with the same Al 2 O 3 procedure as used for the heterostructure wafers was measured to be 10 11 cm -2 eV -1 at mid-gap by using the conductance method. 34,35 Simulations incorporating D it (not shown in this paper)…”

Section: Measurement and Experimental Detailsmentioning

confidence: 99%

Extraction of large valence-band energy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostructures on relaxed SiGe substrates

et al. 2012

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MOS-capacitors were fabricated on type II staggered gap strained-Si/strained-Ge heterostructures epitaxially grown on relaxed SiGe substrates of various Ge fractions. Quasistatic quantum mechanical capacitance-voltage (CV) simulations were fit to experimental CV measurements to extract the band alignment of the strained layers. The valence band offset of the strained-Si/strained-Ge heterostructure was found to be 770, 760, and 670 meV for 35, 42, and 52% Ge in the relaxed SiGe substrate, respectively. These values are approximately 100 meV larger than expected on the basis of the usually recommended band offsets for modeling Si/Ge structures. It is shown that the larger valence band offsets found here are consistent with an 800 meV average valence band offset between Si and Ge, which also explains the type II band alignment observed in strained-Si 1-x Ge x on unstrained-Si heterostructures.

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“…In particular Ge is of major interest as both electron and hole mobilities are considerably larger compared to Si (5). This has been recently verified in strained Ge-pFETs (4,5). However, due to the lower band gap and higher dielectric constant of Ge, bulk Ge devices suffer from high leakage currents and short channel effects.…”

Section: Introductionmentioning

confidence: 79%

Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

et al. 2014

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We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.

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High Hole-Mobility Strained-$\hbox{Ge/Si}_{0.6} \hbox{Ge}_{0.4}$ P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness

Cited by 39 publications

References 8 publications

High mobility high-κ-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs

High mobility high-κ-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs

Extraction of large valence-band energy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostructures on relaxed SiGe substrates

Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

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High Hole-Mobility Strained-$\hbox{Ge/Si}_{0.6} \hbox{Ge}_{0.4}$ P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness

Cited by 39 publications

References 8 publications

High mobility high-&#x03BA;-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs

High mobility high-&#x03BA;-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs

Extraction of large valence-band energy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostructures on relaxed SiGe substrates

Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

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High mobility high-κ-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs

High mobility high-κ-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs