High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed

Druais, G.; Dilliway, G.; Fischer, P.; Guidotti, E.; Lühn, Ole; Radisic, Aleksandar; Zahraoui, S.

doi:10.1016/j.mee.2008.06.004

Cited by 27 publications

(13 citation statements)

References 8 publications

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“…The dielectric layer, which is often made of silicon dioxide with 1~2 ȝm thickness, provides a barrier for the silicon substrate against Cu diffusion. Similar to the Cu damascene interconnects, the barrier layer is usually made of metallic materials such as Ti, Ta, and their respective nitrides, TiN and TaN, with a thickness less than 0.1 ȝm [20][21][22]. FEA was performed and found that the relatively thin barrier layer has little effect on the thermal stresses and the interfacial fracture driving force, but it may play an important role by enhancing the interfacial adhesion [23].…”

Section: Tsv With Dielectric Buffer Layersmentioning

confidence: 99%

Stress-Induced Delamination Of Through Silicon Via Structures

Ryu¹,

Lu²,

Im³

et al. 2011

AIP Conference Proceedings

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Articles you may be interested inMicro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for threedimensional interconnects J. Appl. Phys. 111, 063513 (2012); 10.1063/1.3696980Micro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon via J. Appl. Phys. 110, 073517 (2011) Abstract. Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently threedimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.

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Section: Tsv With Dielectric Buffer Layersmentioning

confidence: 99%

Stress-Induced Delamination Of Through Silicon Via Structures

Ryu¹,

Lu²,

Im³

et al. 2011

AIP Conference Proceedings

View full text Add to dashboard Cite

show abstract

“…The dielectric layer, which is often made of silicon dioxide with 1~2 μm thickness, provides insulation of the TSV from the silicon substrate. Similar to the Cu damascene interconnects, the barrier layer is usually made of metallic materials such as Ti, Ta, and their respective nitrides, TiN and TaN, with a thickness less than 0.1 μm [20][21][22]. The relatively thin barrier layer has little effect on the thermal stresses and the interfacial fracture driving force, but it may play an important role by enhancing the interfacial adhesion [18].…”

Section: Effects Of Dielectric Buffer Layersmentioning

confidence: 99%

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

Ryu

Zhang

et al. 2010

AIP Conference Proceedings

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“…At present, SiN x by the plasma enhanced CVD (PECVD) method is used as the insulating barrier [2], and Ta, Ti, and other metal films [7] or TiN x film [8] are utilized as the diffusion barrier. However, because inferior film quality and barrier property are found as a result of reducing the temperature, and thus formation of films possessing distinguished barrier property and film quality even at low temperatures is desirable.…”

Section: Introductionmentioning

confidence: 99%

Low‐Temperature Deposition of Reactively Sputtered SiN_x Films Applicable to TSV Process

Sato

Takeyama

Kobayashi

et al. 2016

Elect Comm in Japan

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In the through silicon via (TSV) process, which is a key technology for a three-dimensional large-scale integration (LSI), particularly in the "via-last process," SiN x films of high density are urgently needed for fabrication at low deposition temperatures. However, it is generally known that a SiN x film prepared at low temperatures shows low film density, resulting in poor insulating barrier properties. As a solution to this issue, we propose the use of the SiN x films deposited by reactive sputtering. We can obtain sputtered SiN x films at high density (2.78 to 2.99 g/cm 3 ) in spite of deposition without substrate heating. The 20-nmthick SiN x films passed an experimental check on barrier properties with respect to Cu diffusion upon annealing at 700°C for 1 h. The films also show good step coverage for a TSV with an aspect ratio of 1.5. The SiN x films prepared by reactive sputtering are a candidate for a good insulating barrier applicable to the via-last TSV process. C⃝ 2016 Wiley Periodicals, Inc. Electron Comm Jpn, 99(9): 101-107, 2016; Published online in Wiley Online Library (wileyonlinelibrary.com).

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High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed

Cited by 27 publications

References 8 publications

Stress-Induced Delamination Of Through Silicon Via Structures

Stress-Induced Delamination Of Through Silicon Via Structures

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

Low‐Temperature Deposition of Reactively Sputtered SiN_x Films Applicable to TSV Process

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High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed

Cited by 27 publications

References 8 publications

Stress-Induced Delamination Of Through Silicon Via Structures

Stress-Induced Delamination Of Through Silicon Via Structures

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

Low‐Temperature Deposition of Reactively Sputtered SiNx Films Applicable to TSV Process

Contact Info

Product

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Low‐Temperature Deposition of Reactively Sputtered SiN_x Films Applicable to TSV Process