2007
DOI: 10.1088/0957-4484/18/35/355307
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High aspect ratio silicon nanomoulds for UV embossing fabricated by directional thermal oxidation using an oxidation mask

Abstract: Nanomoulding is simple and economical but moulds with nanoscale features are usually prohibitively expensive to fabricate because nanolithographic techniques are mostly serial and time-consuming for large-area patterning. This paper describes a novel, simple and inexpensive parallel technique for fabricating nanoscale pattern moulds by silicon etching followed by thermal oxidation. The mask pattern can be made by direct photolithography or photolithography followed by metal overetching for submicron- and nanos… Show more

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Cited by 8 publications
(10 citation statements)
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References 14 publications
(13 reference statements)
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“…The bottom part of the silicon mold turned out to be wider compared to the top part after the LOCOS process. This was mainly due to the isotropic oxidation at the corner of the silicon nanoridge, and it affected the size of the top part of the formed nanochannel after nanoimrpinting (Chen et al 2007). If needed, aspect ratio higher than 1:5.5 can also be achieved by reducing the pattern widths on the photomask or by carefully controlling the LOCOS process time.…”
Section: Resultsmentioning
confidence: 99%
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“…The bottom part of the silicon mold turned out to be wider compared to the top part after the LOCOS process. This was mainly due to the isotropic oxidation at the corner of the silicon nanoridge, and it affected the size of the top part of the formed nanochannel after nanoimrpinting (Chen et al 2007). If needed, aspect ratio higher than 1:5.5 can also be achieved by reducing the pattern widths on the photomask or by carefully controlling the LOCOS process time.…”
Section: Resultsmentioning
confidence: 99%
“…If needed, aspect ratio higher than 1:5.5 can also be achieved by reducing the pattern widths on the photomask or by carefully controlling the LOCOS process time. Figure 3c shows that the resulting sidewalls of the silicon nanoridges had low surface roughness owing to the anisotropic KOH etching along the silicon crystalline geometry when compared with other Si etching technique such as deep reactive ion etching (DRIE) (Chen et al 2007;Liang et al 2007). Generally, DRIE leaves sidewalls with corrugation or scallop shapes, because of the nature of the process sequence that is cycled between etching and passivation phases (Nilsson et al 2003).…”
Section: Resultsmentioning
confidence: 99%
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“…Further applications include field emission electrodes [39,40] and quantum dots [41][42][43]. Silicon stamps for nanoimprint lithography have also been extensively explored [44][45][46][47][48][49][50][51].…”
Section: Introductionmentioning
confidence: 99%
“…Here we presented a top-down fabrication technique for wafer-scale and high aspect ratio nanochannel preparation. Edge lithography, [25][26][27] a MEMS technique compatible fabrication approach, was utilized to define aluminium nanogaps, instead of chromium ones 27 due to the better etching controllability of the aluminium etchant. High aspect ratio nanochannels were then fabricated by deep reactive ion etching (DRIE) with so-prepared aluminium patterns as the etching mask.…”
Section: Introductionmentioning
confidence: 99%