Hierarchical timing analysis using conditional delays

Abstract

We present a novel method to perform timing analysis of hierarchical circuits. It is based on the representation of circuit modules by conditional delay matrices (CDMs) which combine module delays with event propagation conditions. The CDM model is independent of module complexity and allows automatic identijication of false paths. We exploit hierarchy information to p e~o r m eflcient delay computation. The effectiveness of the method is demonstrated on a high-level model of the ISCAS-85 circuit ~6 2 8 8 , which is difJicult to analyze using traditional approaches. The method has been implemented in a symbolic timing analysis program called CAI: The application of CAT to carry-skip adders shows that hierarchical timing analysis is faster by an order of magnitude than gate-level analysis.

Verification of Large Systems in Silicon

“…As is clear in the work of the Virtual Socket Interface (VSI Alliance, 1996), this is more straightforward the closer to the physical implementation one gets: there are good standards for much of the physical characterization of the behavior of a chip and associated constraints, at the gate level. However, as indicated by the work of Yalcin and Hayes (1995), there are significant problems in aggregating component-level timing characteristics so that meaningful margins survive at the block-level. We believe that it is the ability to characterize and estimate these margins with high quality that is the key element in assuring a clean, predictable and successful handover from the system-level design entity to the implementation entity.…”

A hierarchical approach towards system level static timing verification of SoCs

“…It is a divide and conquer approach which often leads to a much faster system level validation. Scheffer, in [11], has shown that if proper grouping can be made, then the complexity of a timing analysis of combinational circuits has been shown to be faster than gate-level analysis in some previous works [9]. In this paper, at first, the requirements for a hierarchical system level timing verification of a core-based design − such as an SoC − have been explored, and then an algorithm for hierarchical timing verification is proposed.…”

Functional timing analysis for IP characterization

“…Recent characterization methods have used functional analysis to improve timing accuracy [5,10]. Functional timing analysis captures the fact that the delays in a circuit are strongly linked to the way the circuit functions.…”

“…Two widely used methods for functional timing analysis are symbolic evaluation via binary decision diagrams (BDDs) [10] and Boolean search that systematically performs an implicit enumeration of the input space [1,9]. Both methods assume that the delays of a circuit depend on the values of all of its inputs.…”