Functional timing analysis for IP characterization

Yalcin, Hakan; Mortazavi, Mohammad; Palermo, Robert; Bamji, Cyrus; Sakallah, Karem A.

doi:10.1145/309847.310045

Cited by 7 publications

(2 citation statements)

References 9 publications

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“…For this reason, no assumption about the arrival times at the inputs should be made. On the contrary, the maximum input-output delays M ij in (12) are exclusively timing characteristics of the module.…”

Section: Timing Model Formulationmentioning

confidence: 99%

“…In the black-box style, the input-output delay matrix of a module is directly used to represent its timing information. To reduce the size of the delay matrix, the assumption made in [10]- [12] that the timing of a module is mainly determined by a subset of the inputs (control signals) of the module can be applied. Contrary to using the delay matrix directly, the gray-box style method transforms the original netlist to a much smaller one by discarding structural details but maintaining the same input-output delays.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On hierarchical statistical static timing analysis

Li¹,

Chen²,

Schmidt³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the correlation between delays of circuit components, timing model generation and hierarchical timing analysis face more challenges than in static timing analysis. In this paper, a novel method to generate timing models for combinational circuits considering variations is proposed. The resulting timing models have accurate input-output delays and are about 80% smaller than the original circuits. Additionally, an accurate hierarchical timing analysis method at design level using pre-characterized timing models is proposed. This method incorporates the correlation between modules by replacing independent random variables to improve timing accuracy. Experimental results show that the correlation between modules strongly affects the delay distribution of the hierarchical design and the proposed method has good accuracy compared with Monte Carlo simulation, but is faster by three orders of magnitude. I. INTRODUCTIONAs the feature size of semiconductor devices scales to the deep sub-micron realm, parameter variations have stronger impact on circuit performance. These variations make traditional corner-based static timing analysis (STA) too pessimistic. Therefore, statistical static timing analysis (SSTA) is introduced to analyze circuit performance statistically. In SSTA, cell delays are modeled as functions of random variables representing process parameters with variations. Then, arrival times are propagated to compute the circuit delay. Unlike the result of STA, the circuit delay in SSTA is a distribution providing delay-yield information to designers.Linear models are proposed in [1]- [3], where cell delays are modeled as linear functions of Gaussian random variables. This assumption simplifies the arrival time propagation algorithm at the expense of accuracy. To improve modeling and propagation accuracy, the canonical linear form in [2] is extended in [4] to handle nonlinear and non-Gaussian parameters. With the same purpose, quadratic models are proposed in [5]-[8]. It is also pointed out in [7] that their method can be in a general polynomial form with the tradeoff between runtime and accuracy. Another method to improve timing accuracy is proposed in [9], where delays are modeled as linear functions of Gaussian and non-Gaussian random variables. The latter are identified by independent component analysis.Similar to migrating from transistor level to cell level, the hierarchical design style is adopted for more abstraction to overcome increasing design complexities. In a hierarchical design flow, a design is composed of a series of modules at different levels. In designs using IP (Intellectual Property)

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Section: Timing Model Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On hierarchical statistical static timing analysis

Li¹,

Chen²,

Schmidt³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

Fast and accurate timing characterization using functional information

Yalcin

Mortazavi

Palermo

et al. 2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Timing macro-modeling of IP blocks with crosstalk

Chen

Zhou

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

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With the increase of design complexities and the decrease of minimal feature sizes, IP reuse is becoming a common practice while crosstalk is becoming a critical issue that must be considered. This paper presents two macro-models for specifying the timing behaviors of combinational hard IP blocks with crosstalk effects. The gray-box model keeps a coupling graph and lists the conditions on relative input arrival time combinations for couplings not to take effect. The black-box model stores the output response windows for a basic set of relative input arrival time combinations, and computes the output arrival time for any given input arrival time combination through the union of some combinations in the basic set. Both macro-models are conservative, and can greatly reduce the pessimism existing in the conventional "pin-to-pin" model. This is the first work to deal with timing macromodeling of combinational hard IP blocks with the consideration of crosstalk effects. IntroductionWith the progress of deep sub-micron technologies, shrinking geometries have led to a reduction in self-capacitance of wires. Meanwhile coupling capacitances have increased as wires have a larger aspect ratio and are brought closer together. For present day processes, the coupling capacitance can be as large as the sum of the area capacitance and the fringing capacitance, and the trends indicate that the role of coupling capacitance will be even more dominant in the future as feature sizes shrink. This makes crosstalk a major problem in IC design. Crosstalk introduces noise between adjacent wires, and even alters the functions of circuits. If an aggressor and a victim switch simultaneously on the same direction, the victim will speed up. Likewise, if an aggressor and a victim switch on the opposite directions, the victim will slow down.With the growing complexity of VLSI systems, the intellectual property (IP) reuse is becoming a common practice. There are previous researches dealing with the timing macromodeling of IP blocks, and all of them are based on the concept of path delay [1,2,3,4,5,6]. The simplest of such models is the "pin-to-pin" delay model used to characterize standard cells and other complex combinational circuits. For example, given a simple combinational circuit shown in Figure 1(a), its "pin-to-pin" delay model is shown in Figure 1(b). The numbers shown on each arc give the minimal and maximal delays from one pin to another. In this case, if a(x) and A(x) are used to represent the earliest and latest arrival time of signal x, respectively, we haveTo model a sequential circuit with memory elements, the "pinto-pin" model is extended to include timing constraints from a clock pin to an input pin (to model setup and hold conditions) and delay arcs from a clock pin to an output pin (to model the latch output to circuit output delay) [1]. Functionality may also be used to reduce the pessimism in these models [5,6]. * This work was supported by NSF under CCR-0238484. Unfortunately, coupling totally destroys the path delay...

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Functional timing analysis for IP characterization

Cited by 7 publications

References 9 publications

On hierarchical statistical static timing analysis

On hierarchical statistical static timing analysis

Fast and accurate timing characterization using functional information

Timing macro-modeling of IP blocks with crosstalk

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