Two new trends are emerging in the design and production of very large integrated systems on silicon: on the one hand technology that enables a new opportunity for trade in encapsulated intellectual property cast into re-usable blocks for system-level use and, on the other, the partition of the vertical flow from high-level design through to manufacture into at least three separate businesses -the system design house, the IP provider and the silicon implementation house. While the situation appears to be similar to that which prevailed at lower scales of integration (e.g. TTL and boards), the complexity and scale of the new systems and their components pose interesting challenges for designers and the businesses in which they operate. This paper considers, in particular, the challenges that relate to design and verification flow and some possible consequences for the evolution and use of HDLs.
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