Hierarchical SoC testing scheduling based on the ant colony algorithm

Cui, Xiaole; Wei, Cheng; Yin, Liang; Sun, Yachun; Zhou, Yan

doi:10.1109/asicon.2009.5351198

Cited by 2 publications

(8 citation statements)

References 16 publications

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“…Column 1 in Table 12 represents the different SOCs. Column 3 represents earlier works [19, 21, 22, 24, 25] and our work in six rows for each SOC. Columns 4, 5, 6, 7, 8, 9 and 10 represent the results of test times in the number of clock cycles (#CC) with respect TAM widths 16, 24, 32, 40, 48, 56 and 64, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…Addressing Problem III, several power-aware SOC test scheduling strategies have been done in [19][20][21][22][23][24][25]31]. In [19], the rectangular 3D bin-packing approach has been applied to solve the SOC test scheduling problem under power constraint.…”

Section: Problem To Be Solvedmentioning

confidence: 99%

“…An integer linear programming-based solution is presented in [31]. Another test scheduling algorithm based on the ant colony optimisation [31] algorithm heuristic is presented in [24], where the objective is to reduce the total test time with the condition that the peak power and TAM Bus do not exceed certain limits. The power-constrained test scheduling is documented in [25] where shuffle frog leaping algorithm (SFLA) is associated with the Bin-Packing algorithm.…”

Section: Problem To Be Solvedmentioning

confidence: 99%

“…A number of cores in SOCs d695, p22810, p34392 and p93791 are 10, 28, 19 and 32, respectively. For each SOC, the TAM widths chosen have seven instances 16,24,32,40,48,56 and 64. Columns 3, 4, 5 and 6 depict TSV limits in a 3D partition as reported in [31][32][33][34], while our work considering the partitions, B ≤ 4 and B ≤ 8 for Columns 7 and 8 depict the TSV limit.…”

Section: Problem IImentioning

confidence: 99%

“…Power droops induce clock stretching which may lead to a good chip incorrectly failing a timing test [18]. Therefore, power-aware test strategies are very much needed for efficient test power management and many researchers have worked on this issue [16][17][18][19][20][21][22][23][24][25][26][27]. In this paper, we address this issue.…”

Section: Introductionmentioning

confidence: 99%

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Approach of genetic algorithm for power‐aware testing of 3D IC

Kaibartta

Giri

Rahaman

et al. 2019

IET Computers & Digital Techniques

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The interconnect between the cores of System-on-Chip (SOC) degrades the circuit performance by contributing to circuit delay and power consumption. To reduce this problem, SOC-based three-dimensional (3D) integrated circuit (IC) technology as a promising solution where multiple layers are stacked together decreasing the length of interconnect. However, 3D IC invites some new problems including more complexity in test generation. Testing of 3D IC requires test access architecture called Test Access Mechanism (TAM) for the purpose of transport of test stimuli to the cores placed in different layers. During testing due to increasing switching activity, any circuit demands higher power consumption and it becomes more acute for 3D IC. Moreover, testing of 3D ICs has other constraints. In this study, the authors address the issue of 3D IC testing using genetic algorithm-based approach to decrease test time. At first, available TAM width is partitioned into some fixed groups and they have to find partitioning of TAM and distribution of cores among layers with a goal to decrease test time. Next, they do the same considering, variable partitions with or without certain power limits. Experimental results establish the efficacy of the authors' method.

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