HIBI v.2 Communication Network for System-on-Chip

Salminen, Erno; Lahtinen, Vesa; Kangas, Tero; Riihimäki, Jouni; Kuusilinna, Kimmo; Hämäläinen, Timo D.

doi:10.1007/978-3-540-27776-7_43

Cited by 13 publications

(9 citation statements)

References 8 publications

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“…The IP interfaces communicate with the software processor via a specific bus/transfer protocol. In most cases the IPs are not directly connected to the bus: there is a conversion mechanism to adapt to the specific protocol [14] [15]. IPs are then interconnected via the software processor for the control of the entire application.…”

Section: Software Processor Approachmentioning

confidence: 99%

Requirements for Interfacing IP-Components in Re-configurable Platforms

Lemaitre

Alliot

Deprettere

2006

J VLSI Sign Process Syst Sign Image Video Technol

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When mapping large and high-throughput signal processing applications onto heterogeneous platforms, parts of these applications are assigned to re-configurable components. Automating such mappings without delving deep into details implies the (re-) use of IP components. When it comes to 1) relying on IP components in systemlevel and (re-configurable) platform-based design, and 2) porting of such designs across platforms, it is not well known how to integrate both IP libraries and portability requirements into the design flow. To investigate these uncertainties, we have conducted four case studies around the (re-)use and interfacing of IP components. One is focusing on the porting issue, one is dealing with a new automated task-level mapping method, one is evaluating a HW-SW commercially available co-design method, and one is about standardization of interfaces for IP wrapping. The case studies reveal the weakness of otherwise highly desirable system-level design methods when evaluated with respect to fast, accurate, and systematic IP integration.

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Section: Software Processor Approachmentioning

confidence: 99%

Requirements for Interfacing IP-Components in Re-configurable Platforms

Lemaitre

Alliot

Deprettere

2006

J VLSI Sign Process Syst Sign Image Video Technol

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“…The components and tools used in this work are listed in Table 1 [11]. The architecture configuration tool automates the platform hardware generation using a library of RTL descriptions of hardware components.…”

Section: Introductionmentioning

confidence: 99%

Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications

Arpinen

Kukkala

Salminen

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0. The platform is comprised of multiple Altera Nios II softcore processors and custom hardware accelerators connected by the Heterogeneous IP Block Interconnection (HIBI) communication architecture. Each processor has a local copy of eCos real-time operating system for the scheduling of multiple application threads. The mapping of a UML application into the proposed platform is presented by distributing a WLAN medium access control protocol onto multiple CPUs. The experiments performed on FPGA show that our approach raises system design to a new level. To our knowledge, this is the first real implementation combining a high-level design flow with a synthesizable platform.

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“…The system is benchmarked and compared with the same architecture with no GALS support to analyze the pros and cons of the GALS. The GALS communication is provided by Heterogeneous IP Block Interconnection (HIBI) [2] that has a special mixed-clock FIFO interface for asynchronous links. The FIFO has the same signaling interface as a synchronous FIFO, thus no modifications are required for the IP blocks.…”

Section: Introductionmentioning

confidence: 99%

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA

Kulmala

Hämäläinen

Hännikäinen

2006

2006 International Conference on Field Programmable Logic and Applications

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Globally Asynchronous Locally Synchronous (GALS) is a paradigm for complexity management and re-use of large System-on-Chip (SoC) architectures.GALS is most often based on specific ASIC design components or special FPGA platforms with custom development tools. In this paper we present a multiprocessor GALS implementation on a standard commercial FPGA with standard development tools.The key building block is a novel, reliable RTL mixed clock FIFO. A complete MPEG-4 video encoder with four processors is implemented for proofing the concept. The area overhead compared to a fully synchronous design is shown to be only 2% and the performance overhead is 3%. This is negligible compared to the benefits that are much better flexibility, ASIC or FPGA vendor independency, and reduced design time. Furthermore, the mixed-clock interfaces allow easy re-usability, since the RTL-level blocks do not need to be re-verified in design iterations.

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HIBI v.2 Communication Network for System-on-Chip

Cited by 13 publications

References 8 publications

Requirements for Interfacing IP-Components in Re-configurable Platforms

Requirements for Interfacing IP-Components in Re-configurable Platforms

Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA

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