This paper presents the design and implementation of a unique multi-radio Wireless Sensor Network (WSN) platform compared to current WSN nodes that have only one radio interface. Four independent, low energy radio transceivers allow simultaneous reception and transmission to either another multi-radio WSN node or up to four different WSN nodes. This also enables high interference tolerance, low latency, and high mesh-networking performance. The platform is based on synthesizable multiprocessor System-on-Chip implementation on FPGA. The radios are compatible with ultra-low energy microcontroller based WSN nodes, which can be freely mixed in the network. The platform applicability is demonstrated by an ultra low latency WSN router and high data rate file transfer applications. Theoretical hop delay is as low as 106 μs, while 3.3 Mbps network throughput is achievable. Performance measurements for up to four parallel Nios II softcore processors are also presented.
This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0. The platform is comprised of multiple Altera Nios II softcore processors and custom hardware accelerators connected by the Heterogeneous IP Block Interconnection (HIBI) communication architecture. Each processor has a local copy of eCos real-time operating system for the scheduling of multiple application threads. The mapping of a UML application into the proposed platform is presented by distributing a WLAN medium access control protocol onto multiple CPUs. The experiments performed on FPGA show that our approach raises system design to a new level. To our knowledge, this is the first real implementation combining a high-level design flow with a synthesizable platform.
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