HfZrO<sub>&lt;italic&gt;x&lt;/italic&gt;</sub>-Based Ferroelectric Synapse Device With 32 Levels of Conductance States for Neuromorphic Applications

Oh, Seungyeol; Kim, Sang Woo; Kwak, Myunghoon; Song, Jeonghwan; Woo, Jiyong; Jeon, Sanghun; Yoo, In-Kyeong; Hwang, Hyunsang

doi:10.1109/led.2017.2698083

Cited by 220 publications

(179 citation statements)

References 12 publications

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“…55 In our device structure, weights are defined through the intermediate states of the channel resistance, enabled via the multi-domain nature of the ferroelectric HZO layer. 25,29,56 By switching only a subset of the domains, a state between R ON and R OFF can be set. 29 The fraction of the switched ferroelectric domains FeFET showed stable retention properties for 18 differentiable channel resistances (>4bit) for the full 1500 s. The good retention measurement hints to an absence of depolarization or other screening mechanisms.…”

Section: Resultsmentioning

confidence: 99%

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights

Halter

Bégon‐Lours

Bragaglia

et al. 2020

ACS Appl. Mater. Interfaces

102

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Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are non-volatile synaptic elements such as memristors. Key memristor properties include a suitable non-volatile resistance range, continuous linear resistance modulation and symmetric switching. In this work, we demonstrate voltage-controlled, symmetric and analog potentiation and depression of a ferroelectric Hf 0.57 Zr 0.43 O 2 (HZO) field effect transistor (FeFET) with good linearity. Our FeFET operates with a low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been done over 4-bits depth with low noise (1 %) in the tungsten oxide (WO x ) read out channel. By adjusting the channel thickness from 15nm to 8nm, the on/off ratio of the FeFET can be engineered from 1 % to 200 % with an on-resistance ideally >100 kΩ, depending on the channel geometry. The device concept is using earth-abundant materials, and is 1 arXiv:2001.06475v1 [cs.ET] 17 Jan 2020 compatible with a back end of line (BEOL) integration into complementary metal-oxidesemiconductor (CMOS) processes. It has therefore a great potential for the fabrication of high density, large-scale integrated arrays of artificial analog synapses.Keywords ferroelectric switching, hafnium zirconium oxide, tungsten oxide, BEOL, ferroelectric field-effect transistor, memristor

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Section: Resultsmentioning

confidence: 99%

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights

Halter

Bégon‐Lours

Bragaglia

et al. 2020

ACS Appl. Mater. Interfaces

102

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“…To gain a resistance change by ferroelectric switching, one should adopt a ferroelectric field-effect transistor (FeFET) structure with three terminals, where the change in dielectric polarization causes a 5 variation in the resistance of the FeFET channel [35]. The resistance change in the FeFET thus enables inmemory computing elements such as neuromorphic synapses [36].…”

Section: Computational Memory Technologiesmentioning

confidence: 99%

In-memory computing with resistive switching devices

2018

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Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and timeconsuming data movement that plagues current designs. Here we review the development of inmemory computing using resistive switching devices, where the two-terminal structure of the devices and the direct data processing in the memory can enable area-and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing.

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“…The multidomain polarization switching capability of polycrystalline HZO (hafnium–zirconium–oxide) thin film can be utilized to tune the FeFET threshold voltage which in turn can modulate FeFET channel conductance. The FeFET channel's multiconductance levels can be used to record synaptic weight . Recently, Jerry et al demonstrated an FeFET‐based synaptic device using Hf 0.5 Zr 0.5 O 2 (HZO) as ferroelectric material .…”

Section: Ferroelectric Field‐effect Transistormentioning

confidence: 99%

Emerging Memory Devices for Neuromorphic Computing

Upadhyay

Jiang

Wang

et al. 2019

Adv Materials Technologies

360

229

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the modern computers are still largely based on the von Neumann architecture, and designed as a general-purpose machine, which make computers useful and convenient to use, but they are highly inefficient for data intensive tasks. The bus connecting memory and processor becomes a bottleneck for data transfer, referred to as the von Neumann bottleneck. [3] To improve the performance of computing systems in the so-called "big data" era, we must fundamentally change the way we compute today. Instead of being compute-centric, we should transgress to a data-centric paradigm.Neuroscientists and psychologists, all around the world have been studying the functional architecture of the human brain for centuries, which inspired datacentric computing methods such as artificial neural networks (ANNs) and machine learning (ML). The human brain can be characterized by its massive parallel reconfigurable connections (synapses or memory) connecting billions of neurons (the main processing unit). [4] Synapses play a very important role in achieving learning and adaptability of the human brain. The weight of a synapse shows connection strength between the two neurons linked by that synapse. In the learning phase, the synaptic weight changes in an analog fashion based on the learning rules. [5] ML and ANNs use a high-level abstract concept of human cognition and are referred to as brain-inspired computing. To further leverage and exploit the potential advantages and capabilities of the human brain, we may need to more faithfully mimic its functionality on hardware. Emerging devices that can be used for such neuromorphic computing with different levels of brain-inspiration will be our topic of discussion in this paper.In recent years, neuromorphic computing has emerged as a promising technology for the post-Moore's law era. Neuromorphic computing systems are highly connected and parallel, consume relatively low power and process in memory. To implement a neuromorphic system on hardware, it is important to realize: (1) artificial neurons that mimic biological neurons and (2) artificial synapses that emulate biological synapses, both of which must be power-efficient, scalable, and capable of implementing relevant learning rules to facilitate large-scale neuromorphic functions. To this end, over the last few years, numerous efforts have been made to realize artificial synapses using post-CMOS devices, including resistive randomaccess memory (ReRAM) (drift [6] and diffusive [7] memristors), A neuromorphic computing system may be able to learn and perform a task on its own by interacting with its surroundings. Combining such a chip with complementary metal-oxide-semiconductor (CMOS)-based processors can potentially solve a variety of problems being faced by today's artificial intelligence (AI) systems. Although various architectures purely based on CMOS are designed to maximize the computing efficiency of AI-based applications, the most fundamental operations including matrix multiplication and convolution heavily rely on the CMOS-based m...

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HfZrO_{<italic>x</italic>}-Based Ferroelectric Synapse Device With 32 Levels of Conductance States for Neuromorphic Applications

Cited by 220 publications

References 12 publications

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights

In-memory computing with resistive switching devices

Emerging Memory Devices for Neuromorphic Computing

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HfZrO<italic>x</italic>-Based Ferroelectric Synapse Device With 32 Levels of Conductance States for Neuromorphic Applications

Cited by 220 publications

References 12 publications

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights

Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights

In-memory computing with resistive switching devices

Emerging Memory Devices for Neuromorphic Computing

Contact Info

Product

Resources

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HfZrO_{<italic>x</italic>}-Based Ferroelectric Synapse Device With 32 Levels of Conductance States for Neuromorphic Applications