Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem

Abstract

Abstract-Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power consumption and low cost. With the rapid evolution of telecom standards and the increasing demand for multi-standard products, the need for flexible baseband solutions is growing. The concept of Multi-Processor System-on-Chip (MPSoC) is well adapted to enable hardware reuse between products and between multiple wireless standards in the same device. Heterogeneous architectures are well known solutions but they have limited flexibility.Based on the experience of two heterogeneous Software Defined Radio (SDR) telecom chipsets, this paper presents the homoGENEous Processor arraY (GENEPY) platform for 4G applications. This platform is built with Smart ModEm Processors (SMEP) interconnected with a Network-on-Chip. The SMEP, implemented in 65nm low-power CMOS, can perform 3.2 GMAC/s with 77 GBits/s internal bandwidth at 400MHz. Two implementations of homogeneous GENEPY are compared to a heterogeneous platform in terms of silicon area, performance and power consumption. Results show that a homogeneous approach can be more efficient and flexible than a heterogeneous approach in the context of 4G Mobile Terminals.

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

“…This approach has been leveraged for software-defined radio applications (see for example Ramacher et al [37], CEA MAGALI [9,23] and StepNP [31]), in high-performance computing (for example by Maxeler [33]) and in the embedded vision domain (for example Vortex [29,40] for biologically-inspired vision acceleration, and NeuFlow [19] and nn-X [20], which focus on Convolutional Neural Network acceleration). Loose coupling of processors and accelerators through messagepassing channels is extremely scalable and power-efficient, as accelerators completely bypass the Von Neumann bottleneck, working only when they are fed with input.…”

Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory

“…We have used a simulation platform called GENEPY [12] to estimate the latency of the proposed algorithm applied at software level; also we have targeted a hardware implementation through a dedicated module to evaluate implementation cost in terms of area.…”

“…The homogeneous GENEPY platform is a MPSoC based on a telecom baseband processor [12], called a SMEP unit. This unit exploits a high degree of parallelism by separated hardware for external communications (Network Interface), internal communications (data mover), data storage (Smart Memory Engine), processing tasks (DSP cluster) and management (Control Processor).…”

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

“…The following algorithm ensures that Eqs. (4) and (5) are met for each local port of the nodes used by the application to be mapped.…”