Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory

Mansouri, Imen; Jalier, Camille; Clermidy, Fabien; Benoit, Pascal; Torres, Lionel

doi:10.1109/isvlsi.2010.61

Cited by 4 publications

(4 citation statements)

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“…It represents 0.4% of a VFI's power consumption. The reference VFI is a basic unit of GENEPY MPSoC SMEP [3] [9] also designed for the ST CMOS 65nm kit.…”

Section: Resultsmentioning

confidence: 99%

“…Including connections, a cluster of the (W-L) sub-network occupies 73475µm² of silicon area and a cluster of the (f) sub-network 18369µm². This represents 3% of the area of a VFI [3].…”

Section: Resultsmentioning

confidence: 99%

“…This is acceptable considering all the huge gains in terms of speed (×4500 compared to [3]) and energy consumption (÷6800 compared to [3]) this solution offers, Table I.…”

Section: Resultsmentioning

confidence: 99%

“…It has been shown to reduce the MPSoC temperature by 23% [1] or the energy consumption by 38% [2]. However, the time response of the control unit provides a solution for (V dd ,f) from few µs to hundreds of µs (at clock frequencies from 100 to 500 MHz) [1] [3]. This time response increases with number of VFIs in the MPSoC.…”

Section: Introductionmentioning

confidence: 99%

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Analog encoded neural network for power management in MPSoC

Larras

Boguslawski

Lahuec

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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Encoded neural networks mix the principles of associative memories and error-correcting decoders. This paper introduces an analog implementation of this new type of network to manage the power distribution in Multiprocessor System-on-Chip (MPSoC). The proposed circuit has been designed for the 1V supply ST CMOS 65nm process, with a low complexity and low power consumption (less than 1% of the MPSoC power). Compared to a digital counterpart based on game theory, this analog solution consumes 6800 times less energy and reacts 4500 times faster. Thus, this analog circuit allows to fully exploiting DVFS circuits switching capabilities to continuously adapt the power distribution of an MPSoC.I.

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“…It represents 0.4% of a VFI's power consumption. The reference VFI is a basic unit of GENEPY MPSoC SMEP [3] [9] also designed for the ST CMOS 65nm kit.…”

Section: Resultsmentioning

confidence: 99%

“…Including connections, a cluster of the (W-L) sub-network occupies 73475µm² of silicon area and a cluster of the (f) sub-network 18369µm². This represents 3% of the area of a VFI [3].…”

Section: Resultsmentioning

confidence: 99%

“…This is acceptable considering all the huge gains in terms of speed (×4500 compared to [3]) and energy consumption (÷6800 compared to [3]) this solution offers, Table I.…”

Section: Resultsmentioning

confidence: 99%