Providing multiple hard latency and throughput guarantees for packet switching networks on chip

Heisswolf, Jan; König, Ralf; Kupper, Martin; Becker, J.

doi:10.1016/j.compeleceng.2013.06.005

Cited by 39 publications

(20 citation statements)

References 37 publications

(37 reference statements)

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“…In the context of CAP, such end-to-end connections are used to improve performance and reduce communication overhead on behalf of the application programmer. The proposed NoC realizes a fully decentralized and scalable resource allocation scheme as detailed in [11]. All virtual channels can be either used by Best Effort (BE) communication or GS end-to-end connections.…”

Section: Resource Allocationmentioning

confidence: 99%

Cap

Heisswolf

Zaib

Zwinkau

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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Networks on Chip (NoC) come along with increased complexity from the implementation and management perspective. This leads to higher energy consumption and programming complexity of NoC architectures. This work introduces communication aware programming to address communication resource management and efficient programming of NoC architectures. A programming interface is introduced to express communication requirements at the language level. These requirements are evaluated by an operating system component, which configures the communication hardware accordingly. The proposed concept enables an intuitive use of NoC features like end-to-end connections and Direct Memory Access (DMA). The presented results show that communication aware programming can improve performance and energy consumption.

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Section: Resource Allocationmentioning

confidence: 99%

Cap

Heisswolf

Zaib

Zwinkau

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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“…It comprises 16 SPARC LEON3 processing elements that are available as part of GRLIB [18], equally distributed over 4 tiles that in turn are connected via a custom-designed network-on-chip [19]. The platform is prototyped on multiple FPGAs (Synopsys CHIPit System [20] consisting of six Xilinx Virtex-5 XC5VLX330 FPGAs) and runs at a frequency of 50 MHz.…”

Section: Evaluation Platformmentioning

confidence: 99%

Self-adaptive corner detection on MPSoC through resource-aware programming

Paul

Oechslein

Erhardt

et al. 2015

Journal of Systems Architecture

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“…As a remedy, physical links between adjacent routers in our proposed NoC architecture are arbitrated in a weighted round robin scheme [12] for transmitting the packets of the different messages routed over it. In this arbitration scheme, also an amount of time slots (one slot for transmitting one packet) is periodically available for the overall transmission over a link, and a budget of time slots can be reserved for the transmission of a single message.…”

Section: Timing Analysis On Network-on-chipmentioning

confidence: 99%

“…However, in contrast to a global synchronous TDMA, only the amount of time slots and not their positions within one period are fixed. This enables dynamic system management and increases the utilization while still allowing to compute upper bounds for worst-case response times [12].…”

Section: Timing Analysis On Network-on-chipmentioning

confidence: 99%

Invasive computing for timing-predictable stream processing on MPSoCs

Wildermann

Bäder

Bauer

et al. 2016

It - Information Technology

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Multi-Processor Systems-on-a-Chip (MPSoCs) provide sufficient computing power for many applications in scientific as well as embedded applications. Unfortunately, when real-time requirements need to be guaranteed, applications suffer from the interference with other applications, uncertainty of dynamic workload and state of the hardware. Composable application/architecture design and timing analysis is therefore a must for guaranteeing real-time applications to satisfy their timing requirements independent from dynamic workload. Here, Invasive Computing is used as the key enabler for compositional timing analysis on MPSoCs, as it provides the required isolation of resources allocated to each application. On the basis of this paradigm, this work proposes a hybrid application mapping methodology that combines designtime analysis of application mappings with run-time management. Design space exploration delivers several resource reservation configurations with verified real-time guarantees for individual applications. These timing properties can then be guaranteed at run-time, as long as dynamic resource allocations comply with the offline analyzed resource configurations. This article describes our methodology and presents programming, optimization, analysis, and hardware techniques for enforcing timing predictability. A case study illustrates the timing-predictable management of real-time computer vision applications in dynamic robot system scenarios.

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Providing multiple hard latency and throughput guarantees for packet switching networks on chip

Cited by 39 publications

References 37 publications

Cap

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Self-adaptive corner detection on MPSoC through resource-aware programming

Invasive computing for timing-predictable stream processing on MPSoCs

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