Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications

Kwon, Jung-Hyok; Chang, Ik Joon; Lee, In-Soo; Park, Heemin; Park, Jongsun

doi:10.1109/tcsi.2012.2185335

Cited by 59 publications

(41 citation statements)

References 15 publications

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“…5. HETROGENOUS SRAM Jinmo Kwon [6] presents a heterogeneous SRAM sizing approach for the embedded memory of H.264 video processor, where the more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. As a result, the failure probabilities significantly decrease for the SRAM cells storing the more important bits, which allow us to obtain the better video quality even in lower voltage [6].…”

Section: Decoupled Read/write Modementioning

confidence: 99%

A Review on Low Power Sram

2017

IJRTER

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Abstract-The main issue in VLSI design are optimizing speed, scaling in silicon technology and increased packing density. These issues account for increased power dissipation in SoC (System on Chips) making them unsuitable for portable operations. Since SRAM consist of almost 60% of VLSI circuits, hence, it is needed that a low power SRAM design to maximize the run time with minimum requirements on size, battery life and weight allocated to batteries. In this paper the basic operation of SRAM along with techniques to reduce total power dissipation are discussed.

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Section: Decoupled Read/write Modementioning

confidence: 99%

A Review on Low Power Sram

2017

IJRTER

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“…Based on the analysis in Section II A, four internal SRAMs are considered for resizing the SRAM cell. The failure probability of an SRAM increases as the normalized SRAM bit-cell size decreases [6].…”

Section: B the Proposed Selection Schemementioning

confidence: 99%

“…The appropriate SRAM cell size is selected for each SRAM considering the area limitation. To decide proper SRAM cell size, S AVER is assumed to 1.5× width bit-cell [6]. The cell size larger than S AVER is selected for the most sensitive SRAM, "Curr_SRAM", whereas the cell size smaller than S AVER is selected for the most insensitive SRAM, "Ref_SRAM_Y".…”

Section: B the Proposed Selection Schemementioning

confidence: 99%

An adaptive selection of an SRAM cell size for power reduction in an H.264/AVC encoder

Kim

Chang

Lee

2016

2016 IEEE International Conference on Consumer Electronics (ICCE)

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Voltage scaling is a widely used technique to reduce a power consumption of a static random access memory (SRAM) but it may cause an SRAM failure. In order to reduce power consumption without significant quality loss, this paper proposes a novel method to select the appropriate SRAM cell sizes in an H.264/AVC encoder according to the sensitivities to the quality loss caused by SRAM failures. Experimental results show that the proposed scheme achieves a significant PSNR improvement, an average of 2.2dB at 900 mV operation, compared to the identical selection of SRAM cell sizes.

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“…This problem also exists in frequency-scaling technique. In [10], the bitcell size is adjusted to match the capacitance, which also needs large effort due to the special design. Different from the accurate operation to all the bitcells above, in the field of image processing, errors in different bit-positions of a pixel will lead to different output quality of a processed image.…”

Section: Introductionmentioning

confidence: 99%

A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

Yang

Huang

Chen

et al. 2016

IEICE Electron. Express

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By adopting the human visual system property, a priority-based selective bit dropping strategy to reduce DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) power consumption is presented in this paper. The tradeoff between power consumption and output quality is explored as well. During the data flow in image processing, the original image data are first processed with our proposed strategy, from which the number of bit-'1' in lower part of each pixel is reduced. Then the approximate data are pushed into the DRAM and SRAM for further computation, where the refresh power consumption for DRAM is reduced due to the less bit-'1' in each data and the write power consumption for SRAM is also reduced due to the lower switch probability in write operation. The proposed strategy has been realized with digital logic circuits and the approximate image data are processed by the Discrete Cosine Transform (DCT) in simulation. The results show that 27.7% refresh power reduction on average for DRAM can be achieved and the SRAM also obtained 21.7% write power reduction with negligible overhead. As for the final output quality of the images, only 1.01 dB losses for Peak-Signal-Noise-Ratio (PSNR) is presented (about 3% lower than accurate processing) after the DCT processing.

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Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications

Cited by 59 publications

References 15 publications

A Review on Low Power Sram

A Review on Low Power Sram

An adaptive selection of an SRAM cell size for power reduction in an H.264/AVC encoder

A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

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