Heterogeneous multiprocessor for the management of real-time video and graphics streams

Strik, M.; Timmer, A.H.; Meerbergen, J. van; Waterlander, E.; Harmsze, F.; Vaassen, Ad; Sevat, L.; Oosterhuis, M.; Rootselaar, G.J. van; Herten, H. van; Jaspers, E.G.T.; Janssen, J.G.W.M.; Essink, G.; Leijten, J.

doi:10.1109/4.881220

Cited by 33 publications

(15 citation statements)

References 10 publications

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“…Examples are embedded devices hosting multimedia applications [14] or applications that demand audio signal processing [12]. Many of these low-power HeMP systems are also real-time systems [15] in each task must complete its execution by its deadline to avoid any critical failure. For this reason, the problem of minimizing the energy consumption without missing any deadline has become an important issue in constructing low-power realtime HeMP systems.…”

Section: Introductionmentioning

confidence: 99%

A Near-optimal Solution for the Heterogeneous Multi-processor Single-level Voltage Setup Problem

Huang

Tsai

Chu

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Section: Introductionmentioning

confidence: 99%

A Near-optimal Solution for the Heterogeneous Multi-processor Single-level Voltage Setup Problem

Huang

Tsai

Chu

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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“…The authors in [27] explored the use of a heterogeneous system in a real-time video and graphics streams management system, while in [32], the authors applied an adaptive job assignment scheme to perform data partitioning for a multiprocessor implementation of MPEG2 video encoding. A heterogeneous multiprocessor (five cores) for HDTV systems was developed in [10].…”

Section: Related Workmentioning

confidence: 99%

Design methodology for pipelined heterogeneous multiprocessor system

Shee

Parameswaran

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g. SMP) and application specific architectures (i.e. DSP, ASIC). ASIPs have emerged as a viable alternative to conventional processing entities (PEs) due to its configurability and programmability. In this work, we introduce a heterogeneous multi-processor system using ASIPs as processing entities in a pipeline configuration. A streaming application is taken and manually broken into a series of algorithmic stages (each of which make up a stage in a pipeline). We formulate the problem of mapping each algorithmic stage in the system to an ASIP configuration, and propose a heuristic to efficiently search the design space for a pipeline-based multi ASIP system.We have implemented the proposed heterogeneous multiprocessor methodology using a commercial extensible processor (Xtensa LX from Tensilica Inc.). We have evaluated our system by creating two benchmarks (MP3 and JPEG encoders) which are mapped to our proposed design platform. Our multiprocessor design provided a performance improvement of at least 4.11X (JPEG) and 3.36X (MP3) compared to the single processor design. The minimum cost obtained through our heuristic was within 5.47% and 5.74% of the best possible values for JPEG and MP3 benchmarks respectively.

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“…Strik et al (5) explored the use of a heterogeneous system in a real-time video and graphics streams management system, while Zhang and Wu (6) applied an adaptive job assignment scheme to perform data partitioning for a multiprocessor implementation of MPEG2 video encoding. A heterogeneous multiprocessor (five cores) for HDTV systems was developed in Berić et al (7) .…”

Section: Related Workmentioning

confidence: 99%

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

Shee

Erdos

Parameswaran

2007

Int J Parallel Prog

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Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive realtime systems and video / image encoding devices. These system are commonly deployed to overcome deadline misses, which are primarily due to overloading of a single multitasking core. In this paper, we explore the use of multiple cores for a single application, as opposed to multiple applications executing in a parallel fashion. A single application is parallelized using two different methods: one, a master-slave model; and two, a sequential pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues as the means of communications between two cores. In a master-slave model, we utilized a course grained approach whereby a main core distributes the workload to the remaining cores and reads the processed data before writing the results back to file. In the pipeline model, a lower * National ICT Australia is funded through the Australian Government's Backing Australia's Ability initiative, in part through the Australian Research Council. granularity is used. The application is partitioned into multiple sequential blocks; each block representing a stage in a sequential pipeline. For both models we applied a number of differing configurations ranging from a single core to a nine-core system. We found that without any optimization for the seven core system, the sequential pipeline approach has a more efficient area usage, with an area increase to speedup ratio of 1.83 compared to the masterslave approach of 4.34. With selective optimization in the pipeline approach, we obtained speed ups of up to 4.6× while with an area increase of only 3.1× (area increase to speedup ratio of just 0.68).

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Heterogeneous multiprocessor for the management of real-time video and graphics streams

Cited by 33 publications

References 10 publications

A Near-optimal Solution for the Heterogeneous Multi-processor Single-level Voltage Setup Problem

A Near-optimal Solution for the Heterogeneous Multi-processor Single-level Voltage Setup Problem

Design methodology for pipelined heterogeneous multiprocessor system

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

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