Heterogeneous Multiprocessor for High Definition Video

Beric, A.; Sethuraman, Ramanathan; Pinto, C.A. Alba; Peters, H.; Veldman, G.; Haar, Peter van de; Duranton, Marc

doi:10.1109/icce.2006.1598480

Cited by 15 publications

(3 citation statements)

References 5 publications

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“…The authors in [27] explored the use of a heterogeneous system in a real-time video and graphics streams management system, while in [32], the authors applied an adaptive job assignment scheme to perform data partitioning for a multiprocessor implementation of MPEG2 video encoding. A heterogeneous multiprocessor (five cores) for HDTV systems was developed in [10].…”

Section: Related Workmentioning

confidence: 99%

Design Methodology for Pipelined Heterogeneous Multiprocessor System

Shee¹,

Parameswaran²

2007

2007 44th ACM/IEEE Design Automation Conference

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Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g. SMP) and application specific architectures (i.e. DSP, ASIC). ASIPs have emerged as a viable alternative to conventional processing entities (PEs) due to its configurability and programmability. In this work, we introduce a heterogeneous multi-processor system using ASIPs as processing entities in a pipeline configuration. A streaming application is taken and manually broken into a series of algorithmic stages (each of which make up a stage in a pipeline). We formulate the problem of mapping each algorithmic stage in the system to an ASIP configuration, and propose a heuristic to efficiently search the design space for a pipeline-based multi ASIP system.We have implemented the proposed heterogeneous multiprocessor methodology using a commercial extensible processor (Xtensa LX from Tensilica Inc.). We have evaluated our system by creating two benchmarks (MP3 and JPEG encoders) which are mapped to our proposed design platform. Our multiprocessor design provided a performance improvement of at least 4.11X (JPEG) and 3.36X (MP3) compared to the single processor design. The minimum cost obtained through our heuristic was within 5.47% and 5.74% of the best possible values for JPEG and MP3 benchmarks respectively.Hardware/software partitioning, architecture, ASIP

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Section: Related Workmentioning

confidence: 99%

Design Methodology for Pipelined Heterogeneous Multiprocessor System

Shee¹,

Parameswaran²

2007

2007 44th ACM/IEEE Design Automation Conference

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“…These flexible combinations make MPSoC systems very powerful and be able to implement complex functions with high performance and low power by integrating multiple heterogeneous processors, hierarchy memory systems, custom logic, and on-chip interconnection. With such advantages, MPSoC architecture has been widely applied in various fields such as network [24], multimedia [20,25,28] and HDTV [9]. We focus on the MPSoC design and synthesis for real-time signal processing for biomedical applications in this paper.…”

Section: Introductionmentioning

confidence: 99%

Design and Synthesis of a Multiprocessor System-on-Chip Architecture for Real-Time Biomedical Signal Processing in Gamma Cameras

Sun

Wang

Shao

et al. 2008

J Sign Process Syst Sign Image Video Technol

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MPSoC (Multi-Processor System-on-Chip) architecture is becoming increasingly used because it can provide designers much more opportunities to meet specific performance and power goals. In this paper, we propose an MPSoC architecture for implementing realtime signal processing in gamma camera. Based on a fully analysis of the characteristics of the application, we design several algorithms to optimize the systems in terms of processing speed, power consumption, and area costs etc. Two types of DSP core have been designed for the integral algorithm and the coordinate algorithm, the key parts of signal processing in a gamma camera. An interconnection synthesis algorithm is proposed to reduce the area cost of the Network-on-Chip.We implement our MPSoC architecture on FPGA, and synthesize DSP cores and Network-on-Chip using Synopsys Design Compiler with a UMC 0.18 μm standard cell library. The results show that our technique can effectively accelerate the processing and satisfy the requirements of real-time signal processing for 256 × 256 image construction.

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“…Strik et al (5) explored the use of a heterogeneous system in a real-time video and graphics streams management system, while Zhang and Wu (6) applied an adaptive job assignment scheme to perform data partitioning for a multiprocessor implementation of MPEG2 video encoding. A heterogeneous multiprocessor (five cores) for HDTV systems was developed in Berić et al (7) .…”

Section: Related Workmentioning

confidence: 99%

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

Shee

Erdos

Parameswaran

2007

Int J Parallel Prog

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Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive realtime systems and video / image encoding devices. These system are commonly deployed to overcome deadline misses, which are primarily due to overloading of a single multitasking core. In this paper, we explore the use of multiple cores for a single application, as opposed to multiple applications executing in a parallel fashion. A single application is parallelized using two different methods: one, a master-slave model; and two, a sequential pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues as the means of communications between two cores. In a master-slave model, we utilized a course grained approach whereby a main core distributes the workload to the remaining cores and reads the processed data before writing the results back to file. In the pipeline model, a lower * National ICT Australia is funded through the Australian Government's Backing Australia's Ability initiative, in part through the Australian Research Council. granularity is used. The application is partitioned into multiple sequential blocks; each block representing a stage in a sequential pipeline. For both models we applied a number of differing configurations ranging from a single core to a nine-core system. We found that without any optimization for the seven core system, the sequential pipeline approach has a more efficient area usage, with an area increase to speedup ratio of 1.83 compared to the masterslave approach of 4.34. With selective optimization in the pipeline approach, we obtained speed ups of up to 4.6× while with an area increase of only 3.1× (area increase to speedup ratio of just 0.68).

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Heterogeneous Multiprocessor for High Definition Video

Cited by 15 publications

References 5 publications

Design Methodology for Pipelined Heterogeneous Multiprocessor System

Design Methodology for Pipelined Heterogeneous Multiprocessor System

Design and Synthesis of a Multiprocessor System-on-Chip Architecture for Real-Time Biomedical Signal Processing in Gamma Cameras

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

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