Design Methodology for Pipelined Heterogeneous Multiprocessor System

Shee, Seng Lin; Parameswaran, Sri

doi:10.1109/dac.2007.375276

Cited by 11 publications

(3 citation statements)

References 17 publications

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“…We obtained a six processor JPEG encoder benchmark produced by Shee et al in [18] (using the Tensilica's toolset) for our experimentation. The partitioned JPEG program (pipeline of processors) was mapped in Xtensa LX2 using the design flow shown in Figure 1.…”

Section: Experimental Setup and Resultsmentioning

confidence: 99%

Shield

Patel

Parameswaran

2008

Proceedings of the 45th Annual Design Automation Conference

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Security of MPSoCs is an emerging area of concern in embedded systems. Security is jeopardized by code injection attacks, which are the most common types of software attacks. Previous attempts to detect code injection in MPSoCs have been burdened with significant performance overheads. In this work, we present a hardware/software methodology "SHIELD" to detect code injection attacks in MPSoCs. SHIELD instruments the software programs running on application processors in the MPSoC and also extracts control flow and basic block execution time information for runtime checking.We employ a dedicated security processor (monitor processor) to supervise the application processors on the MPSoC. Custom hardware is designed and used in the monitor and application processors. The monitor processor uses the custom hardware to rapidly analyze information communicated to it from the application processors at runtime. We have implemented SHIELD on a commercial extensible processor (Xtensa LX2) and tested it on a multiprocessor JPEG encoder program. In addition to code injection attacks, the system is also able to detect 83% of bit flips errors in the control flow instructions.The experiments show that SHIELD produces systems with runtime which is at least 9 times faster than the previous solution. SHIELD incurs a runtime (clock cycles) performance overhead of only 6.6% and an area overhead of 26.9%, when compared to a non-secure system.

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Section: Experimental Setup and Resultsmentioning

confidence: 99%

Shield

Patel

Parameswaran

2008

Proceedings of the 45th Annual Design Automation Conference

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“…In particular, stream based multimedia applications are well suited to such a design flow, and they are usually modeled as data flow graphs so that the performance can be estimated or some properties can be verified statically [14], [15]. Also, pipelined parallel execution techniques have been widely used and studied for heterogeneous processors to solve throughput-oriented problems [16]- [18]. Performance and energy consumption tradeoff: There have been many works which focused on multiple objectives such as execution time, energy consumption, reliability, accuracy and so on.…”

Section: Task Mappingmentioning

confidence: 99%

Real-Time and Energy-Efficient Face Detection on CPU-GPU Heterogeneous Embedded Platforms

2018

IEICE Trans. Inf. & Syst.

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As energy efficiency has become a major design constraint or objective, heterogeneous manycore architectures have emerged as mainstream target platforms not only in server systems but also in embedded systems. Manycore accelerators such as GPUs are getting also popular in embedded domains, as well as the heterogeneous CPU cores. However, as the number of cores in an embedded GPU is far less than that of a server GPU, it is important to utilize both heterogeneous multi-core CPUs and GPUs to achieve the desired throughput with the minimal energy consumption. In this paper, we present a case study of mapping LBP-based face detection onto a recent CPU-GPU heterogeneous embedded platform, which exploits both task parallelism and data parallelism to achieve maximal energy efficiency with a real-time constraint. We first present the parallelization technique of each task for the GPU execution, then we propose performance and energy models for both task-parallel and data-parallel executions on heterogeneous processors, which are used in design space exploration for the optimal mapping. The design space is huge since not only processor heterogeneity such as CPU-GPU and big.LITTLE, but also various data partitioning ratios for the data-parallel execution on these heterogeneous processors are considered. In our case study of LBP face detection on Exynos 5422, the estimation error of the proposed performance and energy models were on average −2.19% and −3.67% respectively. By systematically finding the optimal mappings with the proposed models, we could achieve 28.6% less energy consumption compared to the manual mapping, while still meeting the real-time constraint. key words: CPU-GPU heterogeneous execution, performance and energy estimation, task mapping, face detection Chanyoung Oh received the B.S. degree in Electrical and Computer Engineering from the University of Seoul in 2015. He is currently a Ph.D. student in University of Seoul. His research interest includes parallel software design, heterogeneous computing, embedded GPU platforms, computer vision and medical imaging.

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“…In general-purpose computing, heterogeneous multiprocessors are less common. The combinations of heterogeneous multiprocessors pose significant challenges when compared with the symmetric multiprocessor world [13]. Accordingly, acquiring software from many types of processors and making them operate together becomes extremely challenging.…”

Section: Introductionmentioning

confidence: 99%

A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

et al. 2022

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The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems.

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Design Methodology for Pipelined Heterogeneous Multiprocessor System

Cited by 11 publications

References 17 publications

Shield

Shield

Real-Time and Energy-Efficient Face Detection on CPU-GPU Heterogeneous Embedded Platforms

A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

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