Over the past several decades, the aggressive scaling of Si-based metal-oxide-semiconductor field-effect transistor (MOSFET) devices has been successfully achieved. More recently, however, as the technology node approaches its physical limit down to 10 nm regime, alternative methodologies have been made for further extension of the Moore's law, which has mainly focused on implementation of high carrier mobility channel materials. Of various path findings, the advent of graphene, a fascinating two-dimensional (2D) crystal, has received intensive attention, especially due to its massless charge carriers.1,2 Although the absence of intrinsic band gap limits its potential applications as novel channel materials, the discovery of the graphene has spurred the emergence of other material families with the layered structures including transition metal dichalcogenides (MoS 2 , WS 2 and NbSe 2 ), and topological insulators (Bi 2 Te 3 and Bi 2 Se 3 ).
3-7Interestingly, in contrast to the semimetal graphene, MoS 2 as one of the transition metal dichalcogenides has revealed the remarkable potential as the new channel owing to its semiconductor-like bandgap (a direct bandgap of ~1.8 eV for single-layer MoS 2 ), thermal stability, carrier mobility, and compatibility with the CMOS process.4,5 To date, nevertheless, studies on MoS 2 electronics is still in their infancy, since only a few research groups have reported electrical properties of MoS 2 -channel FETs based upon their theoretical predictions and experimental results. 4,[8][9][10] In particular, further enhancement of its mobility is of upmost interest for the channel applicability because monolayer MoS 2 has previously showed poor mobility of < 30 cm 2 /V·S. 5,10,11 Though the field effect mobility could be significantly improved over ~1,000 cm 2 /V·S from the dielectric screening effect by upper high-k dielectric passivation such as Al 2 O 3 and HfO 2 , it still requires more investigation with implementation of much higher permittivity dielectric. 12,13 In this work, therefore, we report properties of single-layer MoS 2 transistor with an epitaxially grown SrTiO 3 (STO) gate dielectric on a Nb-doped STO substrate. Figure 1(a) schematically illustrates the MoS 2 nanosheet transistor. To begin with, the epitaxial STO film with a thickness of ~100 nm was deposited on Nb-doped STO (Nb:STO, Nb content ~1 wt % and resistivity ~0.001 Ω·cm) substrate by using pulsed laser deposition (PLD). To produce an atomically flat surface on the Nb:STO, which serves as a back-gate, it was dipped in a dilute HF solution, followed by high-temperature annealing at 1000°C. 14,15 Then, the Nb:STO substrate had terraces with a uniform interval and step height of about 100 nm and 0.3 nm, respectively, and a very low surface roughness below 0.2 nm. After the 100 nmthick epitaxial STO growth, monolayer MoS 2 sheet was exfoliated from commercially available bulk crystal (SPI Supplies) and then transferred to the STO/Nb:STO substrate. Finally, electrical source/drain (S/D) contacts were fabricated...