HBM3 RAS: Enhancing Resilience at Scale

Gurumurthi, Sudhanva; Lee, Ki-Jun; Jang, Munseon; Sridharan, Vilas; Nygren, Aaron; Ryu, Yesin; Sohn, Kiwon; Kim, Taekyun; Chung, Hoeju

doi:10.1109/lca.2021.3117150

Cited by 14 publications

(8 citation statements)

References 5 publications

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“…In contrast, modern DRAM chips exhibit much higher error rates because technology scaling exacerbates the underlying circuit-level error mechanisms that cause errors [86,142,143,166,167,224,225]. To combat these errors, DRAM producers use stronger error-mitigation mechanisms in modern DRAM chips (e.g., on-die ECC [34,38,40,41,87,115,119,167,224,[226][227][228][229][230], post-package repair [33,34,216,222,223], target row refresh [23,32,45,46], refresh management [34,47]), which are more expensive and incur higher performance and energy overheads.…”

Section: Breakdown Of the Separation Of Concernsmentioning

confidence: 99%

“…Unfortunately, worsening memory reliability remains a serious problem for DRAM consumers, especially high-volume consumers for whom even modest chip error rates are significant at scale [142,221]. Although stronger in-DRAM error mitigations are effective against growing error rates [142,224], they introduce new overheads and challenges for consumers. For example, neither on-die ECC nor target row refresh correct all errors, and the remaining errors (e.g., uncorrectable errors) are difficult for consumers to predict and mitigate because their manifestation depends on the particular on-die ECC and/or TRR mechanism used by a given chip [23,32,38,40,41,46,115,152,229,231].…”

Section: Breakdown Of the Separation Of Concernsmentioning

confidence: 99%

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Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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Section: Breakdown Of the Separation Of Concernsmentioning

confidence: 99%

Section: Breakdown Of the Separation Of Concernsmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…In addition, available theoretical estimations of device performance are given. These values are roughly of the same order of magnitude as the ones in some commercial memory products, [159][160][161][162][163] and therefore can be instructive in guiding future applications. From the table, we can observe that 2D-material-based memory devices have advantages in some aspects, including a lower write/read voltage and power consumption.…”

Section: D Stacking Architecturementioning

confidence: 74%

Circuit‐Level Memory Technologies and Applications based on 2D Materials

Liu

Yang

et al. 2022

Advanced Materials

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random-access memory (DRAMs), static random-access memory (SRAMs), [1] and flash memory, [2] multiple transistors and capacitors are employed to constitute a single functional cell. These functional cells are typically integrated to form a memory array for advanced functionality, miniaturized footprints, low power consumption, and reduced latency. Traditional silicon-based complementary metal-oxidesemiconductor (CMOS) technology has been widely used to build these memory arrays. However, the performance improvement of CMOS-based memory relies on the advance of nanofabrication technology to scale down the feature size of transistors, which is approaching the physical limit. [3] To overcome this bottleneck, emerging memory technologies are brought up as promising supplements to conventional memory devices. [4] These novel types of memory include resistive random-access memory (RRAM), [5,6] ferroelectric RAM (FeRAM), [7] optoelectronic RRAM (ORRAM), [8,9] phase-change memory (PCM), [10] and spin-transfer torque magnetoresistive RAM (STT-MRAM). [11,12] Furthermore, emerging memory devices allow non-von-Neumann architectures that pave the way toward high-performance in-memory computing technology. [13,14] For example, memristive crossbar arrays composed of 1-transistor-1-resistor (1T1R) unit cells can enable in-memory computing and are the most cost-efficient thanks to their two-terminal structure. [15] Advanced 3D monolithic stacking integration also emerges as a promising approach to Memory technologies and applications implemented fully or partially using emerging 2D materials have attracted increasing interest in the research community in recent years. Their unique characteristics provide new possibilities for highly integrated circuits with superior performances and low power consumption, as well as special functionalities. Here, an overview of progress in 2D-material-based memory technologies and applications on the circuit level is presented. In the material growth and fabrication aspects, the advantages and disadvantages of various methods for producing large-scale 2D memory devices are discussed. Reports on 2D-material-based integrated memory circuits, from conventional dynamic random-access memory, static random-access memory, and flash memory arrays, to emerging memristive crossbar structures, all the way to 3D monolithic stacking architecture, are systematically reviewed. Comparisons between experimental implementations and theoretical estimations for different integration architectures are given in terms of the critical parameters in 2D memory devices. Attempts to use 2D memory arrays for in-memory computing applications, mostly on logic-in-memory and neuromorphic computing, are summarized here. Finally, challenges that impede the large-scale applications of 2D-material-based memory are reviewed, and perspectives on possible approaches toward a more reliable system-level fabrication are also given, hopefully shedding some light on future research.

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“…To exacerbate the problem of identifying a de nitive error model, DRAM manufacturers are starting to incorporate two on-die error-mitigation mechanisms that correct a limited number of errors from within the DRAM chip itself: (1) on-die ECC [28,54,95,[254][255][256][257][258] for improving reliability and yield and (2) target row refresh [100,160,222,239] for partially mitigating the RowHammer vulnerability. Prior works on ECC [27,30,54,95,101,258,259,296,[320][321][322][323][324] and RowHammer [92,100,160,226] show that both on-die ECC and TRR change how errors appear outside of the DRAM chip, thereby changing the DRAM error model seen by the memory controller (and therefore, to the rest of the system). Unfortunately, both mechanisms are opaque to the memory controller and are considered trade secrets that DRAM manufacturers will not ofcially disclose [22,23,92,93,95,226,258,298].…”

Section: Lack Of Transparency In Commodity Drammentioning

confidence: 99%

“…Even under con dentiality, DRAM manufacturers may be unwilling to reveal certain proprietary aspects of their designs (e.g., on-die error correction[258,296], target row refresh[92]) or provide speci cally requested numbers.…”

mentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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Mass-produced commodity DRAM is the preferred choice of main memory for a broad range of computing systems due to its favorable cost-per-bit. However, today's systems have diverse system-speci c needs (e.g., performance, energy, reliability) that are di cult to address using one-size-ts-all generalpurpose DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by exploiting slack in access timings to improve performance, or implementing system-level RowHammer mitigations), we observe that designers today lack the necessary insight into commodity DRAM chips' reliability characteristics to implement these techniques in practice. In this work, we make a case for DRAM manufacturers to provide increased transparency into simple device characteristics (e.g., internal row address mapping, cell array organization) that a ect consumer-visible reliability. Doing so has negligible impact on manufacturers given that these characteristics can be reverse-engineered using known techniques; however, it has signi cant bene t for system designers, who can then make informed decisions to be er adapt commodity DRAM to meet modern systems' needs while preserving its cost advantages.To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-speci c design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM access latency; and (4) defending against RowHammer a acks. We observe that adopting solutions for any of the four goals requires system designers to make assumptions about a DRAM chip's reliability characteristics. ese assumptions discourage system designers from using such solutions in practice due to the di culty of both making and relying upon the assumption.We identify DRAM standards as the root of the problem: current standards rigidly enforce a xed operating point with no speci cations for how a system designer might explore alternative operating points. To overcome this problem, we introduce a two-step approach that reevaluates DRAM standards with a focus on transparency of reliability characteristics so that system designers are encouraged to make the most of commodity DRAM technology for both current and future DRAM chips.

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HBM3 RAS: Enhancing Resilience at Scale

Cited by 14 publications

References 5 publications

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Circuit‐Level Memory Technologies and Applications based on 2D Materials

A Case for Transparent Reliability in DRAM Systems

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