Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

Abstract

New hardware security threats are identified in emerging threedimensional (3D) integrated circuits (ICs) and potential countermeasures are introduced. Trigger and payload mechanisms for future 3D hardware Trojans are predicted. Furthermore, a novel, network-on-chip based 3D obfuscation method is proposed to block the direct communication between two commercial dies in a 3D structure, thus thwarting reverse engineering attacks on the vertical dimension. Simulation results demonstrate that the proposed method effectively obfuscates the cross-plane communication by increasing the reverse engineering time by approximately 5× as compared to using direct through silicon via (TSV) connections. The proposed method consumes approximately one fifth the area and power of a typical network-on-chip designed in a 65 nm technology, exhibiting limited overhead.

Towards Energy-Efficient and Secure Computing Systems

“…The communication between Nodes A and B will be modified based on the routing algorithms defined in the NOC-SIP. As reported in [41], the source routing-based NOC-SIP only consumes 21% of the power used in a 2D NoC with the same size. This is because the NOC-SIP does not require implementing the complete NOC router.…”

“…Due to the frequent communication between planes, the application of encryption and decryption is not an energy-efficient approach. The work [41] proposes a network-on-chip-based shielding plane (NOC-SIP) between two planes to thwart reverse engineering attacks in 3D ICs. The countermeasure NOC-SIP shown in Figure 13a obfuscates the communication among the adjacent planes so that attackers have a low success rate to perform sniffing attacks through vertical connection in the 3D chip.…”

Hardware Security For and Beyond CMOS Technology

“…Other works also suggest camouflaging at the system level. For example, [193] proposed to obfuscate the vertical interconnect fabric of 3D ICs by rerouting within dedicated network-on-chip (NoC) chips "sandwiched" between the regular chips. This idea is conceptionally similar to the notion of randomized routing in [185,192], but more flexible, yet also more costly-it seems only warranted in case 3D NoCs are to be employed in any case.…”

3D Integration: Another Dimension Toward Hardware Security

“…Besides LC along with 3D SM as outlined above, other works suggest camouflaging at the system level. More specifically, Dofe et al [24] propose to obfuscate the vertical communication links in 3D ICs by rerouting within dedicated network-on-chip structures (NoCs) "sandwiched" between the chips. In that sense, their idea is similar but more flexible to c 2019 IEEE.…”