Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory

Abstract

Phase Change Memory (PCM) has recently emerged as a promising memory technology. However, PCM's limited write endurance restricts its immediate use as a replacement for DRAM. To extend the lifetime of PCM chips, wear-leveling and salvaging techniques have been proposed. Wear-leveling balances write operations across different PCM regions while salvaging extends the duty cycle and provides graceful degradation for a nonnegligible number of failures.Current wear-leveling and salvaging schemes have not been designed and integrated to work cooperatively to achieve the best PCM device lifetime. In particular, a noncontiguous PCM space generated from salvaging complicates wear-leveling and incurs large overhead. In this article, we propose LLS, a Line-Level mapping and Salvaging design. By allocating a dynamic portion of total space in a PCM device as backup space, and mapping failed lines to backup PCM, LLS constructs a contiguous PCM space and masks lowerlevel failures from the OS and applications. LLS integrates wear-leveling and salvaging and copes well with modern OSes. Our experimental results show that LLS achieves 31% longer lifetime than the state-of-theart. It has negligible hardware cost and performance overhead.

WL-Reviver: A Framework for Reviving any Wear-Leveling Techniques in the Face of Failures on Phase Change Memory

“…For the sake of space efficiency, one must reserve a relatively small amount of additional space once currently reserved space has been used up and failing of a block demands for a shadow block [12], [23]. This means one block used to be mapped into the software's PA address space and was accessible to the software needs to become unreachable.…”

“…Excluding them from the wear leveling can compromise entire PCM chip's leveling efficacy. A more serious issue of the reservation method is that the wear leveling scheme may have to be substantially modified [12], assuming such a modification is possible. Because mapping function of a scheme is designed to accommodate its scheduled data migration, DAs of the reserved blocks, whose data are not involved in the data migration, have to be removed from the functions' target set (or codomain).…”

“…Even worse, some wear-leveling schemes, such as security refresh [16], requires its mapping functions' target set (or mapped DA space) be of size of power of 2 in terms of block count. In this case, the schemes have to resort to mapping table [12] if each reservation did not take away half of a scheme's target set.…”

“…LLS [12] is a scheme sharing a similar goal with WLReviver. It dynamically reduces software-useable address space to acquire reserved space for re-mapping failed blocks.…”

“…Regarding the second question, WL-Reviver needs an additional read when a failed block is accessed by the software. We compare WL-Reviver with LLS [12], a design integrating wear leveling schemes with fault-tolerance solutions to keep wear-leveling from being disrupted upon a block failure, in terms of space loss and time overhead.…”