Guideline for Low-temperature-operation Technique to Extend CMOS Scaling

Hokazono, A.; Kawanaka, S.; Tsumura, Kyosuke; Hayashi, Yuichiro; Tanimoto, Hiroshi; Enda, T.; Aoki, Naofumi; Ohuchi, K.; Inaba, S.; Okano, K.; Fujiwara, M.; Morooka, T.; Goto, Masakazu; Kajita, Akihiro; Usui, Tunemaru; Ishimaru, K.; Toyoshima, Y.

doi:10.1109/iedm.2006.346875

Cited by 7 publications

(5 citation statements)

References 3 publications

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“…However, at low temperatures, the (111) surface of the DG SOI MOSFET has almost the same mobility as the (001) surface of the DG and SG SOI MOSFETs. This is interesting from the viewpoint of low-temperature device applications 34) because it suggests that FinFET devices with (111) surface channels 11,12) are promising for future space applications. 2,18) This point is also very important because it is expected that the DG SOI MOSFET is superior to the SG SOI MOSFET regarding radiation hardness.…”

Section: Resultsmentioning

confidence: 99%

Low-Temperature Behaviors of Phonon-Limited Electron Mobility of Sub-10-nm-Thick Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels

Ōmura

Yamamura

Sato

2009

jjap

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In this study we simulate the impact of silicon layer thickness and temperature on the phonon-limited electron mobility of the inversion layer for ultrathin-body ( 111) and ( 001) surface silicon-on-insulator (SOI) layers in single-gate (SG) and double-gate (DG) SOI metal-oxidesemiconductor field-effect transistors (MOSFETs); one-dimensional self-consistent calculations and relaxation time approximations are performed. For a sub-10-nm-thick SOI layer, it is demonstrated that intra-subband phonon scattering at the lowest subband in the inversion layer on the (111) Si surface of the DG SOI MOSFET is strongly suppressed in a medium-to-high effective field (E eff ) at a low temperature. On the other hand, it is revealed that the contribution of inter-subband phonon scattering in the inversion layer on the (001) Si surface of the DG SOI MOSFET is very large in a medium-to-high E eff regardless of temperature. Simulation results suggest that the phonon-limited electron mobility on the (111) Si surface of the DG MOSFET will be highly advantageous for future high-performance low-temperature device applications including space applications.

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Section: Resultsmentioning

confidence: 99%

Low-Temperature Behaviors of Phonon-Limited Electron Mobility of Sub-10-nm-Thick Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels

Ōmura

Yamamura

Sato

2009

jjap

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“…More importantly, as the temperature is lowered down to 100 K, we observe that these two factors are improved by 70 mV and 88% at the same gate length. As stated earlier, higher mobility can be due to enhanced volume inversion, sub-band splitting, velocity overshoot effect, and reduced phonon scattering [7]- [12]. Whereas higher threshold voltage can be attributed to increase in Fermi potential, low leakage current, reduced latchup susceptibility, and improved gate EI [1], [3]- [5] at lower temperature and lower gate lengths.…”

Section: Gate Length Scalingmentioning

confidence: 98%

“…This improvement is restricted to ∼12 mV at 400 K. We also observe ∼81% improvement in carrier mobility of dual-k FinFET at 100 K against ∼60% at 400 K as compared to lowk FinFET. Improvement in mobility at lower temperature may be attributed to enhanced volume inversion, sub-band splitting, velocity overshoot effect, and reduced phonon scattering [7]- [12]. For a constant current, combined improvement in carrier mobility and V th will enhance the transconductance (g m ) of the device [30].…”

Section: Dual-k Spacer Designmentioning

confidence: 99%

“…The analog performance of the device is enhanced at a low temperature environment because of improved threshold voltage (V th ) due to increase in Fermi potential and improved carrier mobility due to volume inversion, sub-band splitting, reduced phonon scattering, and an enhanced velocity overshoot effect at liquid nitrogen range (≥77 K) [6]- [12].…”

Section: Introductionmentioning

confidence: 99%

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Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths

Nandi

Saxena

Dasgupta

2014

IEEE Trans. Electron Devices

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Higher mobility and smaller subthreshold slope are some attractive features of low-temperature operation of FinFETs at scaled gate lengths. However, very little effort has been made to enhance the analog performance of the device at lower gate lengths. In this paper, we have studied the low temperature analog performance of underlap FinFET at 16-nm gate length. We have observed that for low-temperature analog operation, high-k gate dielectric is not a viable option at this gate length, as the intrinsic dc gain (A V 0 ) decreases with increase in dielectric constant of the gate dielectric because of a pronounced increase in fringeinduced barrier lowering. On the other hand, dual-k spacer-based underlap FinFET is a promising candidate in improving critical analog figures of merit (FOM), such as intrinsic dc gain (A V 0 ), cutoff frequency (f T ), and maximum oscillation frequency (f max ) as the temperature is reduced. More so, the percentage increase in FOM of dual-k FinFET is enhanced at lower temperature as well as at lower gate length. Therefore, dual-k spacer underlap FinFET can be a possible solution for further device scaling at low-temperature environment.Index Terms-Carrier mobility, dual-k spacer, figures of merit (FOM), low-temperature operation.

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“…SCEs such as drain-induced barrier lowering (DIBL), off-state leakage, threshold voltage roll-off and subthreshold slope degradation has posed a crucial challenge to the efforts for down-scaling the CMOS technology [1][2][3][4]. To control SCEs, the vertical surrounding gate (SG) MOSFET [5][6][7][8] becomes one of the promising candidates for improving the subthreshold characteristics as well as packing densities of the very large integrated circuits (VLSI).…”

Section: Introductionmentioning

confidence: 99%

A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs

Chiang

2009

Solid-State Electronics

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Guideline for Low-temperature-operation Technique to Extend CMOS Scaling

Cited by 7 publications

References 3 publications

Low-Temperature Behaviors of Phonon-Limited Electron Mobility of Sub-10-nm-Thick Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels

Low-Temperature Behaviors of Phonon-Limited Electron Mobility of Sub-10-nm-Thick Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels

Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths

A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs

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