Guest Editors' Introduction: Design for Yield and Reliability

Zorian, Y.; Gizopoulos, Dimitris; Vandenberg, C.; Magarshack, Philippe

doi:10.1109/mdt.2004.12

Cited by 43 publications

(16 citation statements)

References 0 publications

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“…3 shows how the column exchange operation is applied on the fat-and-slim, n-m fault tolerant crossbar. We observe that column 6 is the first that covers column 1, so we start by exchanging elements (2,1) and (2,6). For the matrix newly formed, we observe that the first column covered by column 6 is now column 3, so we proceed to exchange elements (4,3) and (4,6).…”

Section: Construction Of Fault Tolerant Global Interconnects Based Onmentioning

confidence: 99%

“…Two different facets can be identified: the first one has its roots in the increasing levels of defect densities that are associated with the continuous feature size shrinking in semiconductor fabrication technology. Chips are more and more prone to defects like shorts and opens caused by particles, contamination, cracks, scratches, and missing vias; photolithography with sub-wavelength feature sizes can result in feature corruption, and chemical mechanical polishing (CMP) may cause surface dishing through over-polishing, ultimately becoming important yield-loss factors [2]. The second aspect is related to the different types of reliability faults that may manifest during the life cycle of the semiconductor chips.…”

Section: Introductionmentioning

confidence: 99%

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NoC Interconnect Yield Improvement Using Crosspoint Redundancy

Grecu

Ivanov

Saleh

et al. 2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Section: Construction Of Fault Tolerant Global Interconnects Based Onmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

NoC Interconnect Yield Improvement Using Crosspoint Redundancy

Grecu

Ivanov

Saleh

et al. 2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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“…Metal layer m One of the well known and highly recommended method to improve via yield/reliability is to add a redundant via adjacent to a single via [15] [17]. Fig.…”

Section: Metal Layer M+1mentioning

confidence: 99%

Post-routing redundant via insertion and line end extension with via density consideration

Lee¹,

Wang²,

Chao³

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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-Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. However, if the amount of inserted redundant vias is not well controlled, it could violate via density rules and adversely worsen the yield and reliability of the design. In this paper, we first study the problem of redundant via insertion, and present two methods to accelerate a state-ofthe-art approach (which is based on a maximum independent set (MIS) formulation) to solve it. We then consider the problem of simultaneous redundant via insertion and line end extension. We formulate the problem as a maximum weighted independent set (MWIS) problem and modify the accelerated MIS-based approach to solve it. Lastly, we investigate the problem of simultaneous redundant via insertion and line end extension subject to the maximum via density rule, and present a two-stage approach for it. In the first stage, we ignore the maximum via density rule, and enhance the MWIS-based approach to find the set of regions which violate the maximum via density rule after performing simultaneous redundant via insertion and line end extension. In the second stage, excess redundant vias are removed from those violating regions such that after the removal, the maximum via density rule is met while the total amount of redundant vias removed is minimized. This density-aware redundant via removal problem is formulated as a set of zero-one integer linear programming (0-1 ILP) problems each of which can be solved independently without sacrificing the optimality. The superiorities of our approaches are all demonstrated through promising experimental results.

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“…Manufacturability must be considered in the design flow. A new research topic, known as design for manufacturability (DFM), has become active recently [1] [2].…”

Section: Introductionmentioning

confidence: 99%

Redundant-via enhanced maze routing for yield improvement

Huang

Pan

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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-Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via after detailed routing. In this paper, we propose the first routing algorithm that considers feasibility of redundant via insertion in the detailed routing stage. Our routing problem is formulated as maze routing with redundant via constraints. The problem is transformed to a multiple constraint shortest path problem, and solved by Lagrangian relaxation technique. Experimental results show that our algorithm can find routing layout with much higher rate of redundant via than conventional maze routing.

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Guest Editors' Introduction: Design for Yield and Reliability

Cited by 43 publications

References 0 publications

NoC Interconnect Yield Improvement Using Crosspoint Redundancy

NoC Interconnect Yield Improvement Using Crosspoint Redundancy

Post-routing redundant via insertion and line end extension with via density consideration

Redundant-via enhanced maze routing for yield improvement

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