NoC Interconnect Yield Improvement Using Crosspoint Redundancy

Abstract

Systems-on-chip integrate increasingly larger numbers of pre-designed cores

Addressing Manufacturing Challenges in NoC-based ULSI Designs

“…In this sense, Table 6.5 shows a complexity comparison of our proposal and the use of spare wires [34]. This table shows the required cross-points to implement both approaches.…”

“…However, when a high number of wires in a link are faulty, performance is severely degraded. Nevertheless, previous proposals where not able to keep the link working in these circumstances while our proposal does [34]. To understand how all the failure patterns can be tolerated with our proposal we should analyze the non-blocking permutations of the Ω −1 network.…”

“…On the contrary, other kind of proposals focus on increasing interconnect yield by using redundant hardware. In this sense, the authors of [34] propose the use of spare wires to tolerate a bounded number of faults without decreasing communication performance.…”

“…Therefore, the distribution of the operating frequency of link wires will be centered at a different frequency for each link (systematic component) and will have a different shape (random component). Actually, random variability data will be useful for tuning mechanisms based on using or not single link wires [34].…”

“…Additionally, according to the predictions of the ITRS [27], defect density levels also increase with technology scaling. Notice that NoC links are specially prone to manufacturing defects, as they are usually routed in the upper metalization layers and require a high number of vias to reach active devices located at the silicon surface [34]. Actually, the probability of having faulty links in a NoC might considerably increase in future CMP systems, expected to be implemented with 22nm technology by 2015 [74] due to the great variability caused by the much smaller transistor size, the increase of defect density levels, and the huge number of links present in the network.…”