Growth of SiGe/Si superlattices on silicon-on-insulator substrates for multi-bridge channel field effect transistors

Growth kinetics of SiGe/Si superlattices on bulk and silicon-on-insulator substrates for multi-channel devices

“…Although (i) the Si gaseous precursors (and thus growth temperatures) and (ii) the SOI substrates are not the same in [10] and in the present study, we do have the same growth temperature drop as the deposited thickness increases from zero up to one hundred nm. The specificity of the present study is (i) to vastly increase the deposited thickness probed (0-800 nm versus 0-200 nm in [10]), this (ii) on more conventional SOI substrates.…”

“…The only comparable study of Si/SiGe superlattices on Si and SOI that we have identified is work we published in 2005. We had then grown at 20 Torr various Si/Si 0.8 Ge 0.2 superlattices (in-between 3 and 5 periods, Si 0.8 Ge 0.2 (Si) layer thickness in-between 14 and 28 nm (9 and 32 nm)) on bulk Si(0 0 1) and un-conventional (100 nm BOX/20 nm Si) SOI substrates [10]. Dichlorosilane and germane were used for the 650 1C growth of the Si 0.8 Ge 0.2 layers and the 700 1C growth of the Si layers.…”

“…The specificity of the present study is (i) to vastly increase the deposited thickness probed (0-800 nm versus 0-200 nm in [10]), this (ii) on more conventional SOI substrates. The adoption of a silane chemistry at 650 1C leads here to a much higher Si growth rate (9.5 nm min À1 on bulk Si(0 0 1)) than in [10] (2.6 nm min À1 ), which should also be most handy in terms of throughput, especially for large number of periods SL.…”

“…Of note are the double-gate [1], the localized silicon-on-insulator (L-SOI) [2], the silicon-on-nothing (SON) [3], the multi-channel (MC) [4,5] and the three-dimensional nano-wires (3D-NW) [6][7][8] devices. They all rely on (i) the (selective) epitaxy of SiGe/Si multilayers [9][10][11], (ii) the anisotropic etching of the active area [12] and (iii) the high degree of selectivity (versus Si) that can be achieved when laterally etching the SiGe layers (with Ge contents above 15%) [13][14][15][16][17]. In the L-SOI and SON approaches, the voids left by the removal of the SiGe buried layer are filled by a Si 3 N 4 /SiO 2 sandwich, leading to the formation of FETs (with localized buried dielectric layers beneath the Si surface channel/gate stacks) that electrically operate in a fully depleted-like regime.…”

Thermoelectric power factor enhancement of AZO/In-AZO quantum well multilayer structures as compared to bulk films

“…We estimate the correlation length from the assumed Gaussian form of the IFR. Previously, it has been reported that the IFR can be neglected in quantum wells over 4.5 nm in width [20], but this is only true for a low level of roughness (<1 nm), which would require a deposition technique other than sputtering. More importantly we believe that it is the ratio of interface roughness to quantum well width that is most important.…”