Growth of InP Layers on Nanometer-Scale Patterned Si Substrates

Bakin, A.; Piester, D.; Behrens, I.; Wehmann, H.-H.; Peiner, Erwin; Ivanov, Alexey; Fehly, D.; Schlachetzki, A.

doi:10.1021/cg025558s

Cited by 21 publications

(11 citation statements)

References 24 publications

(34 reference statements)

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“…In order to satisfy the requirements to be used in InP-based optoelectronic devices as well as low power logic devices with high performance, the high quality epitaxial growth of InP on Si substrates is essentially necessary. Although many research groups have made their efforts to obtain high quality InP for many decades, several problems still remain unresolved due to the considerable lattice constant mismatch (8%), a large difference in thermal expansion coefficient ( 50%) and the generation of polar/non-polar interfaces between InP and Si substrate [4,5]. These challenges are being addressed by the use of III-V buffer layer growth, either on blanket Si wafers [6,7] or on patterned Si wafers [8], which reduces the number of defects degrading the device performances.…”

Section: Introductionmentioning

confidence: 99%

Effects of growth temperature on surface morphology of InP grown on patterned Si(0 0 1) substrates

Lee

Cho

Park

et al. 2015

Journal of Crystal Growth

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Section: Introductionmentioning

confidence: 99%

Effects of growth temperature on surface morphology of InP grown on patterned Si(0 0 1) substrates

Lee

Cho

Park

et al. 2015

Journal of Crystal Growth

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“…Lattice strain relaxation leads to defects and dislocations that propagate through the epitaxial layers at densities approaching 10 9 cm -2 . Considerable progress has been made in reducing the dislocation density to as low as 1.2x10 6 cm -2 using graded buffer layers and strained-layer superlattices (35)(36)(37)(38)(39)(40)(41), thermal cycle annealing (42)(43)(44)(45)(46)(47)(48)(49), and growth on nano-patterned surfaces (50). Fig.…”

Section: Introductionmentioning

confidence: 99%

(Invited) Heterogeneously Integrated III-V on Silicon for Future Nanoelectronics

Hudait

2012

ECS Trans.

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With the scaling of Si CMOS technology, each transistor has become smaller and faster, leading to unprecedented increase in microprocessor performance, while the rising number of transistors increases the power consumption in ICs [1]. The computing power and density of ICs is primarily constrained by power consumption and high-speed operation. Low-power consumption would imply lower heat dissipation, prolonged battery life and reduced cooling requirements, which all add up to significant reductions in cost and energy savings. Going forward transistor scaling will require the introduction of new materials, including III-V and Ge, and novel device architectures to reduce energy consumption. New materials and device structure innovation and their heterogeneous integration on Si could be a key enabler for lowering power consumption and enhance performance of microprocessor. There is a tremendous progress in III-V semiconductor industry in applications ranging from low-power and high-speed computing to photonic devices. Heterogeneous integration of high mobility III-V materials with Si substrate is one of the most promising ways to harvest the potential of III-Vs and prohibit the need for developing large area and expensive III-V wafers. Large lattice mismatch (4-19%) and thermal expansion differences between InAs (InSb) and Si leads to defects and dislocations, which adversely affect the channel mobility and degrades device performance. Although, there has been considerable progress in reducing dislocations using graded buffer, strained superlattices, thermal cycle annealing, and patterned growth; all of them failed to achieve low defect density and eliminate parallel conduction to the channel. Several challenges namely, low growth temperature, elimination of carrier freeze-out at 75K, and scalable buffer elude the successful integration of high-quality III-Vs on Si. To address these challenges, novel material innovations and radical changes in buffer architecture and device design are essential. The InGaAs quantum-well FET structures were heterogeneously integrated on Si substrate to address the low band gap III-V device structures on Si growth issues, and as a potential NMOS channel material for low-power logic. In order to achieve the APD-free III-V buffers on nonpolar Si substrate to address the defects and dislocations due to lattice mismatch and the high-quality InGaAs metamorphic QWFETs device structure growth on such buffer, careful design of various aspects of growth, buffer architecture and strain-relaxation is investigated using MBE. The relaxation state and the buffer layer grading scheme were evaluated using high-resolution x-ray rocking curve, as shown in Fig.

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Section: Introductionmentioning

confidence: 99%

Heterogeneously Integrated III-V on Silicon for Future Nanoelectronics

Hudait

2012

Meet. Abstr.

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Shrinking feature sizes of CMOS transistor has enabled increase in transistor densities and this rising number of transistors increases the power consumption in ICs. Thus, the computing power is primarily constrained by power consumption and high-speed operation. Beyond sub 22 nm technology node, high mobility III-V materials and new device architectures have the potential to provide higher switching speeds and to operate at lower voltage <0.5V than Si FETs. Heterogeneous integration of such high mobility materials with quantum well field effect transistor architecture configuration have recently emerged a promising transistor option for ultra-high speed and low voltage operation. This paper reviews the recent development of the heterogeneous integration of high indium InGaAs quantum well FETs on Si and provide a technological solution for making nanoscale transistors, various integration scheme and solve the physics issues of the origin of defects and dislocations to InGaAs quantum well transistors. As a result, InGaAs quantum well FETs are poised to achieve higher drive current, low-off-state leakage, higher I ON /I OFF ratio, higher f T , controlled short channel effect and thus have a potential for future high-speed and ultra-lowpower electronics.

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Growth of InP Layers on Nanometer-Scale Patterned Si Substrates

Cited by 21 publications

References 24 publications

Effects of growth temperature on surface morphology of InP grown on patterned Si(0 0 1) substrates

Effects of growth temperature on surface morphology of InP grown on patterned Si(0 0 1) substrates

(Invited) Heterogeneously Integrated III-V on Silicon for Future Nanoelectronics

Heterogeneously Integrated III-V on Silicon for Future Nanoelectronics

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