Ground bouncing noise reduction in combinational MTCMOS circuits

Sreenivasulu, P.; Rao, K. Ramakrishna; Babu, A. Vinaya

doi:10.1109/cnt.2014.7062768

Cited by 2 publications

(2 citation statements)

References 15 publications

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“…According to Saxena et al [14], high performance stacking PG structure is implemented to reduce ground bounce noise and leakage current. Sreenivasulu and Rao [15] reported that transistor sizing techniques are adopted to reduce ground bounce noise. Based on literature [16], low leakage multiplier circuit is designed to control ground bounce noise using a stacked sleep transistor with a delayed select signal.…”

Section: Stacking Pg Approachmentioning

confidence: 99%

Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit

Nath

Pradhan

2018

IJE

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The presence of package inductance induces large voltage fluctuation (bounce noise) on the power rail during power down to power up transition in the power gating circuit that may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in active mode. Noise for the architecture has also been analyzed. The effect of various noise minimization approaches for reducing power supply noise have been evaluated in power gating architecture. A new concept of noise minimization technique using Low Dropout Voltage Regulator has been proposed in this paper. The amount of charge in the internal nodes that passes through the sleep transistor during the wake-up transition has been controlled by the proposed noise minimization techniques. The Low Dropout Voltage Regulator is designed with a target of reducing bounce noise by minimizing voltage fluctuations on the power rail. Low noise active mode power gating architectures have been designed in Synopsys Custom Designer tool at iPDK 90nm technology. Saving of noise at the power supply rail has been observed up to 99%.

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Section: Stacking Pg Approachmentioning

confidence: 99%

Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit

Nath

Pradhan

2018

IJE

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“…Although there is decrease in GBN during sleep to active mode of transition, park control results in increase in delay due to twostep switching. Recently a new technique has been presented in literature [13] which uses two sleep transistors and one capacitor. In this approach one transistor gets the sleep signal immediately and the second transistor gets sleep signal after some delay.…”

Section: Introductionmentioning

confidence: 99%

A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

Goyal¹,

Ubhi

Raj

2018

Mathematical Problems in Engineering

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In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.

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Ground bouncing noise reduction in combinational MTCMOS circuits

Cited by 2 publications

References 15 publications

Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit

Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit

A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

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