Summary
This paper presents a highly stable, low leakage inexact full adder (FA) which is based on top gate carbon nanotube field effect transistors (TG‐CNTFET) for motion detector applications. Inexact arithmetic circuits are highly accepted in low power multimedia applications. Circuit level metrics, ie, average power, propagation delay, power‐delay product (PDP), and leakage power dissipation as well as application level metric such as peak signal to noise ratio (PSNR) are considered to compare the performance of proposed inexact FA. All the simulations are performed using HSPICE tool with Stanford 32‐nm TG‐CNTFET model. The operating frequency used for simulation is 1‐Ghz with 0.9‐V supply voltage. Proposed inexact FA successfully achieve manifold reduction in leakage power as well as consume 89.2% lesser energy as compared with latest existing inexact FA while having other parameters in acceptable range. Simulations using MATLAB show satisfactory image quality and PSNR value for motion detection applications. The effect of variations in voltage and temperature on leakage power is also presented which confirms stability of the proposed circuit.
Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are the most important criteria for the fabrication of DSP systems. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, toward higher storage densities. This paper deals with design of low power static random-access memory (RAM) cells and peripheral circuits for standalone RAMs, in 32nm focusing on stable operation and reduced leakage power dissipation. The work is carried out on Tanner Tool version 13 at 32nm technology.
In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.
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