GREDA: A Fast and More Accurate Gate Reliability EDA Tool

Ibrahim, Walid; Beiu, Valeriu; Beg, Azam

doi:10.1109/tcad.2011.2176123

Cited by 21 publications

(7 citation statements)

References 32 publications

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“…The most related works to this paper are several recent studies that explored various analytical ways of computing the overall logic reliability of VLSI logic circuits [23][24][25][26]. Reliability analysis of logic circuits refers to the problem of evaluating the effects of errors due to noise at individual transistors, gates or logic blocks on the outputs of the circuit.…”

Section: Analyzing Fpga Device Reliabilitymentioning

confidence: 99%

Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. Although the idea of scaling V DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT's reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

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Section: Analyzing Fpga Device Reliabilitymentioning

confidence: 99%

Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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“…To the best of our knowledge, there has not been any systematic study on accurately measuring modular criticality values within a large-scale VLSI digital circuit. The most related works to this paper are several recent studies that explored various analytical ways of computing the overall logic reliability of VLSI logic circuits [6][7][8][24][25][26][27][28][29][30][31]. Reliability analysis of logic circuits refers to the problem of evaluating the effects of errors due to noise at individual transistors, gates or logic blocks on the outputs of the circuit, which become magnified when operating at low supply voltage.…”

Section: Contributions and Outlinementioning

confidence: 99%

Stochastically Estimating Modular Criticality in Large-Scale Logic Circuits Using Sparsity Regularization and Compressive Sensing

Alawad

DeMara

Lin

2015

JLPEA

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This paper considers the problem of how to efficiently measure a large and complex information field with optimally few observations. Specifically, we investigate how to stochastically estimate modular criticality values in a large-scale digital circuit with a very limited number of measurements in order to minimize the total measurement efforts and time. We prove that, through sparsity-promoting transform domain regularization and by strategically integrating compressive sensing with Bayesian learning, more than 98% of the overall measurement accuracy can be achieved with fewer than 10% of measurements as required in a conventional approach that uses exhaustive measurements. Furthermore, we illustrate that the obtained criticality results can be utilized to selectively fortify large-scale digital circuits for operation with narrow voltage headrooms and in the presence of soft-errors rising at near threshold voltage levels, without excessive hardware overheads. Our numerical simulation results have shown that, by optimally allocating only 10% circuit redundancy, for some large-scale benchmark circuits, we can achieve more than a three-times reduction in its overall error probability, whereas if randomly distributing such 10% hardware resource, less than 2% improvements in the target circuit's overall robustness will be observed. Finally, we conjecture that our proposed approach can be readily applied to estimate other essential properties of digital circuits that are critical to designing and analyzing them, such as the observability measure in reliability analysis and the path delay estimation in stochastic timing analysis. The only key requirement of our proposed methodology is that these global J. Low Power Electron. Appl. 2015, 5 4 information fields exhibit a certain degree of smoothness, which is universally true for almost any physical phenomenon.

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“…For CMOS gates a transistor sizing method which aims to maximize SNM's has been presented in [5]. For understanding it, we start from the switching probability of a transistor [18]:…”

Section: Maximizing the Static Noise Marginsmentioning

confidence: 99%

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Kharbash

Beiu

Tache

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (V th ) exactly (precise L's) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (V bs ) for having a single L opt for all transistors (as opposed to having two different L opt , one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although V th and L change by ~10%, by using V bs we can still achieve very high SNM's, while additionally reducing power and energy to ~50%.

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GREDA: A Fast and More Accurate Gate Reliability EDA Tool

Cited by 21 publications

References 32 publications

Optimally Fortifying Logic Reliability through Criticality Ranking

Optimally Fortifying Logic Reliability through Criticality Ranking

Stochastically Estimating Modular Criticality in Large-Scale Logic Circuits Using Sparsity Regularization and Compressive Sensing

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

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