Graphene devices, interconnect and circuits &amp;#x2014; challenges and opportunities

“…Such properties provide a strong drive for investigating graphene as a potent contender to Si and to pursue avenues for carbon-based nanoelectronics [10]- [12]. Generally speaking, the main hindrances to graphene-based logic circuitry are design and manufacturing related [13], [14].…”

Section: Introductionmentioning

confidence: 99%

Graphene Nanoribbon Based Complementary Logic Gates and Circuits

Jiang

Laurenciu

Wang

et al. 2019

IEEE Trans. Nanotechnology

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As CMOS feature size is reaching atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, thereby prompting for conducting research on new materials, devices, and/or computation paradigms. Within this context, graphene nanoribbons (GNRs), owing to graphene's excellent electronic properties, may serve as basic structures for carbonbased nanoelectronics. In this paper, we make use of the fact that GNR behavior can be modulated via top/back gate contacts to mimic a given functionality and combine complementary GNRs for constructing Boolean gates. We first introduce a generic gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing its complement. Then, we seek GNR dimensions and gate topologies required for the design of 1-, 2-, and 3-input graphene-based Boolean gates, validate the proposed gates by means of SPICE simulation, which makes use of a non-equilibrium Green's function Landauer formalism based Verilog-A model to calculate GNR conductance, and evaluate their performance with respect to propagation delay, power consumption, and active area footprint. Simulation results indicate that, when compared with 7 nm FinFET CMOS counterparts, the proposed gates exhibit 6× to 2 orders of magnitude smaller propagation delay, 2 to 3 orders of magnitude lower power consumption, and necessitate 2 orders of magnitude smaller active area footprint. We further present full adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of error correcting codes codecs, which outperforms the CMOS equivalent carry-out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits 6.2× smaller delay, 3 orders of magnitude less power consumption, while requiring 2 orders of magnitude less area, when compared with the 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNRbased n-bit ripple carry adder, whose performance is linear in the carry-out path, will be 108× faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to dc-noise characteristics, while performance-wise has a 3.6× smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based

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“…It has also been reported previously that defects can affect the band gap in GNR sheet. 10 Therefore, it is of interest to explore the effect of tailored GNR sheets in the GNRFET channel. The objective of the investigation remains in finding a way to saturate and turn off the transistor.…”

Section: Introductionmentioning

confidence: 99%

Understanding the impact of graphene sheet tailoring on the conductance of GNRFETs

Upadhyay

Choudhary

2015

Bull Mater Sci

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The effect of tailoring the graphene sheets used as channel in a graphene nanoribbon field effect transistor (GNRFET) was investigated. The study was performed using self-consistent solution of Poisson's and Schrodinger's equation in combination with non-equilibrium Green's function (NEGF) formalism. Graphene sheet channel was tailored into different shapes and found that with the introduction of edge roughness along the border of GNR sheet the bandgap of GNRFET channel increases. Tailoring the channel decreases mobility and transmission probability to a great extent and thus the performance of I-V characteristics of GNRFET degrades.

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Graphene devices, interconnect and circuits — challenges and opportunities

Cited by 21 publications

References 13 publications

Influence of Correction Factor on Nearest Neighbour Hopping Parameterin Energy Dispersion Relation of Graphene Nanoribbon

Influence of Correction Factor on Nearest Neighbour Hopping Parameterin Energy Dispersion Relation of Graphene Nanoribbon

Graphene Nanoribbon Based Complementary Logic Gates and Circuits

Understanding the impact of graphene sheet tailoring on the conductance of GNRFETs

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