As CMOS feature size is reaching atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, thereby prompting for conducting research on new materials, devices, and/or computation paradigms. Within this context, graphene nanoribbons (GNRs), owing to graphene's excellent electronic properties, may serve as basic structures for carbonbased nanoelectronics. In this paper, we make use of the fact that GNR behavior can be modulated via top/back gate contacts to mimic a given functionality and combine complementary GNRs for constructing Boolean gates. We first introduce a generic gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing its complement. Then, we seek GNR dimensions and gate topologies required for the design of 1-, 2-, and 3-input graphene-based Boolean gates, validate the proposed gates by means of SPICE simulation, which makes use of a non-equilibrium Green's function Landauer formalism based Verilog-A model to calculate GNR conductance, and evaluate their performance with respect to propagation delay, power consumption, and active area footprint. Simulation results indicate that, when compared with 7 nm FinFET CMOS counterparts, the proposed gates exhibit 6× to 2 orders of magnitude smaller propagation delay, 2 to 3 orders of magnitude lower power consumption, and necessitate 2 orders of magnitude smaller active area footprint. We further present full adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of error correcting codes codecs, which outperforms the CMOS equivalent carry-out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits 6.2× smaller delay, 3 orders of magnitude less power consumption, while requiring 2 orders of magnitude less area, when compared with the 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNRbased n-bit ripple carry adder, whose performance is linear in the carry-out path, will be 108× faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to dc-noise characteristics, while performance-wise has a 3.6× smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based
Designing and implementing artificial systems that can be interfaced with the human brain or that can provide computational ability akin to brain's processing information efficient style is crucial for understanding human brain fundamental operating principles and to unleashing the full potential of brain-inspired computing. As basic neural network components, responsible for information transfer between neurons, artificial synapses able to emulate analog biological synaptic behaviour are of particular interest. State of the art CMOS and memristorbased synapses suffer from scalability drawbacks (large energy consumption and area footprint), variability-induced instability, and are not bio-compatible. In this paper, we propose a generic Graphene Nanoribbon (GNR) based synapse structure and demonstrate that by changing GNR geometry and external bias voltages it can emulate different synaptic plasticity behaviours, i.e., Spike Timing Dependent Plasticity and Long-Term Depression and Potentiation, and that both excitatory and inhibitory synaptic behavior can be obtained with the same GNR geometry. To demonstrate biologically plausible operation, we make use of low voltage bias, i.e., 0.1 V, 0.2 V, and consider inputs consistent with measured brain synapses data, i.e., −50 mV to 50 mV pre-and post-synaptic spikes voltage range, and −60 ms to 60 ms time range. The simulations indicate that by changing the GNR shape we can enrich the plasticity behaviour (potentially beyond the considered cases) and the plasticity change of 100% provided by natural synapses can be achieved. Our investigation clearly suggests that the proposed GNR synapse structure is a promising candidate for large-scale neuromorphic systems integration, which might potentially bring novel insight on brain neurophysiology, as it requires a small footprint, is energy effective, biocompatible, and versatile from the synaptic behaviour point of view.
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