GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications

Yoge, Dhiraj Reddy Nallapa; Chandrachoodan, Nitin

doi:10.1109/vlsid.2012.62

Cited by 21 publications

(20 citation statements)

References 6 publications

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“…Iterative receivers operate on the basis of an iterative exchange of soft information between the various receiver components, which may perform synchronisation [9], channel estimation [10], equalisation [11], demapping [12], turbo decoding [13], LDPC decoding [14] and source decoding [15] The max-log-BCJR algorithm [27] is a reduced-complexity variant of the BCJR that is particularly well suited for implementation. Rather than operating on the basis of bit likelihoods having a high dynamic range, the max-log-BCJR algorithm processes the logarithm of bit likelihood ratios (LLRs), which have a low dynamic range and can be readily represented using fixed-point arithmetic.…”

Section: Bcjr Algorithmmentioning

confidence: 99%

Flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example

Brejza

Maunder

Al-Hashimi

et al. 2017

IET wirel. sens. syst.

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Due to their computational complexity, iterative decoder components such as source and channel decoders are usually implemented using specialized dedicated hardware. This leads to the scenario where each different iterative decoder component of the receiver requires its own hardware. Owing to their relatively high complexity, many capacity-approaching techniques proposed in the literature have not yet been invoked in Wireless Sensor Network (WSN) applications, despite their potential benefits of facilitating a reduced transmission power or extended communication range. Against this background, we propose an energy-efficient architecture comprised of multiple Computation Units (CUs), which is sufficiently flexible for accommodating different iterative decoder components using the same hardware. In this work, the flexible architecture is applied to Joint Source and Channel Coding (JSCC), comprising the Unary Error Correction (UEC) code, a turbo code, and an iterative demodulator. We conceive a flexible technique for controlling the hardware, which supports a high hardwareexploitation ratio for the CUs, reaching a utilization of 88%, compared to 68% achieved in similar solutions reported in the open literature.

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Section: Bcjr Algorithmmentioning

confidence: 99%

Flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example

Brejza

Maunder

Al-Hashimi

et al. 2017

IET wirel. sens. syst.

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“…Further detailed reading on the pre-backward technique is available in [40]. Other windowing techniques include the Previous Iteration Value Initialization (PIVI) technique of [39], [41], which is also known as State-Metric Propagation (SMP) [42]. This avoids the extra computation associated with the pre-backwards step by initializing the windows during the current turbo decoding iteration using the boundary conditions 'inherited' from the previous iteration.…”

Section: Four-level Quantizationmentioning

confidence: 99%

20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

Brejza

Maunder

et al. 2016

IEEE Commun. Surv. Tutorials

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Abstract-During the last two decades, wireless communication has been revolutionized by near-capacity Error-Correcting Codes (ECCs), such as Turbo Codes (TCs), which offer a lower Bit Error Ratio (BER) than their predecessors, without requiring an increased transmission Energy Consumption (EC). Hence, TCs have found widespread employment in spectrum-constrained wireless communication applications, such as cellular telephony, Wireless Local Area Network (WLAN) and broadcast systems. Recently however, TCs have also been considered for energyconstrained wireless communication applications, such as Wireless Sensor Networks (WSNs) and the 'Internet of Things' (IoT). In these applications, TCs may also be employed for reducing the required transmission EC, instead of improving the BER. However, TCs have relatively high computational complexities and hence the associated signal-processing-related ECs are not insignificant. Therefore, when parameterizing TCs for employment in energy-constrained applications, both the processing EC and the transmission EC must be jointly considered. In this tutorial, we investigate holistic design methodologies conceived for this purpose. We commence by introducing turbo coding in detail, highlighting the various parameters of TCs and characterizing their impact on the encoded bit rate, on the Radio Frequency (RF) bandwidth requirement, on the transmission EC and on the BER. Following this, energy-efficient TC decoder ApplicationSpecific Integrated Circuit (ASIC) architecture designs are exemplified and the processing EC is characterized as a function of the TC parameters. Finally, the TC parameters are selected in order to minimize the sum of the processing EC and the transmission EC.

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“…Many studies focus on the receiver end, particularly on the turbo decoder . Lee et al designed the space exploration of the turbo decoding algorithm on GPUs.…”

Section: Introductionmentioning

confidence: 99%

“…Chinnici and Spallaccini designed a novel parallel architecture for GPU, and the turbo decoder was implemented on the architecture. Yoge and Chandrachoodan presented the implementation of a 3GPP standard compliant configurable turbo decoder on a GPU and indicated the challenge in implementing a turbo decoder on a GPU to parallelize log‐MAP decoding algorithm and to perform an architecture‐aware mapping of it onto the GPU. Zhang et al proposed a new implementation of 3GPP LTE standard compliant turbo decoder based on Tesla K20c.…”

Section: Introductionmentioning

confidence: 99%

An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

Wang

et al. 2018

Concurrency and Computation

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The second-generation digital video broadcasting return channel via satellite (DVB-RCS2) is a promising real-time wireless protocol that has been widely used in many applications, such as video conferences, video feeds, and video multicasting. However, the receiver end of DVB-RCS2 is time consuming and should be accelerated by high-performance processing systems. Today, graphic processing units (GPUs) have been applied in communication systems due to high parallel capability and processing throughput. In this study, we design a novel pipeline of the receiver on the CPU-GPU platform. Moreover, we propose a CPU-GPU hybrid strategy to fully utilize resources and reduce communication latency. Compared with the parallel turbo decoder proposed in other work on the same platform, our parallel implementation achieves higher throughput. For the entire DVB-RCS2 receiver, compared with the non-pipelined serial and non-pipelined parallel algorithms, our proposed pipeline obtains 20 times and 6 times speedup, respectively.In addition, the latency of our implementation is lower than that of non-pipelined CPU-GPU implementation, which is equal to 1.06 ms. KEYWORDSCPU-GPU hybrid platform, pipeline, real-time receiver, software defined radio INTRODUCTIONOver the past decade, digital video broadcasting return channel via satellite (DVB-RCS) and its second generation, DVB-RCS2, have gained rapid prominence and support from governments and industries due to low-cost, high-performance, and reliable internet protocol (IP) networks through very small aperture terminals (VSATs). DVB-RCS2 specifies new technology that provides significant advances in time division multiple address (TDMA) performance for improved efficiency, increased throughput, and greater network reliability than DVB-RCS. DVB-RCS2 provides solutions for high-speed Internet access, video services, voice over IP, and global system for mobile communication backhaul used by the maritime industry, energy sector, utility companies, and global corporations. To the best of our knowledge, all services supported by DVB-RCS2 need low latency and high throughput and must provide real-time capability. Although the receive throughput of DVB-RCS2 is important, it cannot achieve high performance on a CPU platform. The graphic processing unit (GPU) provides a new platform to accelerate the wireless applications in software-defined radio. Compared to a CPU, GPU is a highly parallel, multi-threaded, multi-core processor with tremendous computational power and very large memory bandwidth. Thus, GPU is suitable in performing computation-intensive and highly parallel tasks.For convenience, we use the demodulator to represent all modules of the receiver except for the turbo decoder, as shown in Figure 2. By analyzing the running time of each part on the receiver, we find that the decoder is the most time-consuming part, so it has to be accelerated on the CPU-GPU platform. In fact, numerous studies have focused on how to accelerate the turbo decoder using the CPU-GPU platform. [1][2][3][4][5]...

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GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications

Cited by 21 publications

References 6 publications

Flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example

Flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example

20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

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