20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

Abstract

Abstract-During the last two decades, wireless communication has been revolutionized by near-capacity Error-Correcting Codes (ECCs), such as Turbo Codes (TCs), which offer a lower Bit Error Ratio (BER) than their predecessors, without requiring an increased transmission Energy Consumption (EC). Hence, TCs have found widespread employment in spectrum-constrained wireless communication applications, such as cellular telephony, Wireless Local Area Network (WLAN) and broadcast systems. Recently however, TCs have also been considered for energyconstrained wireless communication applications, such as Wireless Sensor Networks (WSNs) and the 'Internet of Things' (IoT). In these applications, TCs may also be employed for reducing the required transmission EC, instead of improving the BER. However, TCs have relatively high computational complexities and hence the associated signal-processing-related ECs are not insignificant. Therefore, when parameterizing TCs for employment in energy-constrained applications, both the processing EC and the transmission EC must be jointly considered. In this tutorial, we investigate holistic design methodologies conceived for this purpose. We commence by introducing turbo coding in detail, highlighting the various parameters of TCs and characterizing their impact on the encoded bit rate, on the Radio Frequency (RF) bandwidth requirement, on the transmission EC and on the BER. Following this, energy-efficient TC decoder ApplicationSpecific Integrated Circuit (ASIC) architecture designs are exemplified and the processing EC is characterized as a function of the TC parameters. Finally, the TC parameters are selected in order to minimize the sum of the processing EC and the transmission EC.

Presentation of an Algorithm for Secure Data Transmission based on Optimal Route Selection during Electromagnetic Interference Occurrence

“…This algorithm is soft-input and soft-output coding. in this paper, to compare and evaluate the effectiveness of the proposed method, The comparison between the Viterbi decoder with the hard-output, soft-output and BCJR algorithm has been performed and the results have been investigated [28], [37]. The complexity of a decoding method is often quantified in terms of the number of operations needed for decoding, which can be described in terms of the number of states or trellis-transitions.…”

“…The complexity of a decoding method is often quantified in terms of the number of operations needed for decoding, which can be described in terms of the number of states or trellis-transitions. Turbo code scheme is introduced in Figure 8 [28], [37]. To design coding software protection, BCJR algorithm and Viterbi decoder are implemented by rate 1/3.…”

Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths

“…Fig. 2 shows the serial LFSR circuit implementation of key polynomial Equation (1). Every exponent of key polynomial is converted into an exclusive-OR gate between input and feedback path.…”

“…This is the reason that CRC is being used in industry for three decades, in spite the fact that more advance techniques for error detection and correction have been developed e.g. Viterbi decoder, low-density paritycheck (LDPC), Reed Solomon and Turbo codes [1], [2], [3], [4].…”

Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths

“…Various forward error correction (FEC) schemes e.g. Low-density parity-check (LDPC), Reed Solomon, Viterbi and Turbo codes are used to meet the growing need to improve the spectrum efficiency [1], [2], [3], [4], [5]. In FEC schemes the encoding of data is done using convolutional encoding and at the receiver end the decoding process is done by viterbi or turbo decoders [21][22][23][24][25][26][27][28][29][30][31].…”