Global Shutter CMOS Image Sensor With Wide Dynamic Range

Belenky, A.; Fish, Alexander; Spivak, A.; Yadid-Pecht, Orly

doi:10.1109/tcsii.2007.908902

Cited by 24 publications

(5 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As opposed to previous DR extension methods (e.g. [4]) where a single-ended signal is compared, the differential signal comparison implemented here reduces the impact of process variations in the correct execution of the algorithm. In case V dif is higher than V th , a "0" is written in the sub-pixel SRAM, indicating that a shorter integration time is required since the pixel value is probably saturated.…”

Section: A Dr Extension and Sub-pixel Operationmentioning

confidence: 99%

A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers

Xhakoni

Gielen

2014

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

This paper presents a global-shutter imager readout architecture which allows a dynamic range of more than 132dB and a high frame rate. It is based on a stacked technology where the top tier contains the back-illuminated pixel array and the bottom one contains the sub-pixel logic array which implements the dynamic range extension by selecting the best integration time for each pixel. Experimental results of a 64 x 64 sub-pixel array confirm the effectiveness of the proposed method in extending the dynamic range by more than 10 bits. The application of the algorithm to higher array resolutions compromises its effectiveness given the increased column capacitance. As a way out, we propose a novel source-follower-based buffer which reduces the settling time of the sub-pixel without increasing its size. The performed analysis shows that the sensor can reach 1900fps and 375fps respectively at full HD and at 8K resolutions.

show abstract

Section: A Dr Extension and Sub-pixel Operationmentioning

confidence: 99%

A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers

Xhakoni

Gielen

2014

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…2, consists of a photodiode connected to a memory driven reset scheme. The photodiode voltage is reset only when the in-pixel memory has been set to '1', according to the dynamic range extension scheme, described in [13]. This pixel consists of a total of 7 nMOS transistors, primarily enabling leakage reduction through the in-pixel memory (M2, M4 and M3) and the readout transistors (N3, N4).…”

Section: Pixel and Sram Cellmentioning

confidence: 99%

An Improved AB<sup>2</sup>C scheme for leakage power reduction in image sensors with on-chip memory

2009

Self Cite

View full text Add to dashboard Cite

Static leakage power is the major component of power consumption in large arrays that operate at a low activity factor. "Smart" image sensors with advanced in-pixel functionality frequently include large on-chip memory arrays for storage of per-pixel data. These systems periodically transfer data from pixels to their corresponding memory bits in a serial access scheme with a relatively low activity factor. Recently, an Adaptive Bulk Biasing Control (AB 2 C) Scheme for leakage reduction in image sensors was presented. In this paper, we introduce an improved AB 2 C scheme that expands the functionality for on-chip memory leakage reduction, in addition to that of the image sensor. In the proposed system, a symmetric voltage distribution is applied around the active row, providing reverse body biasing on deactivated rows to reduce leakage. A test case circuit was implemented in a standard 90nm TSMC process is presented, showing a static power reduction of 26%.

show abstract

“…Wide dynamic range (WDR) image sensors are recently required for a variety of applications including security systems and automobiles. Many techniques for extending their dynamic range based on CMOS image sensor (CIS) technology have been reported [1,2,3,4,5,6,7,8,9,10,11,12]. Toward the goal for developing practically-advantageous WDR image sensors, the WDR technique used in the designed image sensors should maintain important imaging quality factors and functions such as low noise, high sensitivity, high spatial resolution, less motion artifact, wide linear response and flexible control of the dynamic range below its attainable dynamic range.…”

Section: Introductionmentioning

confidence: 99%

A Wide Dynamic Range CMOS Image Sensor with a Charge Splitting Gate and Two Storage Diodes

Seo

Kim

Yasutomi

et al. 2019

Sensors

View full text Add to dashboard Cite

In this paper, a wide dynamic range (WDR) CMOS image sensor (CIS) with a charge splitting gate (SG) and two storage diodes (SDs) is presented. By using single-gate on/off control with the SG, photocurrent path to the first (SD1) or second storage diodes (SD2) is switched alternatively and periodically during exposure and signal electrons generated in a photodiode (PD) are transferred to and accumulated in the SD1 or SD2. By setting a large ratio of the off-time to on-time of the SG, two different sensitivity signals, which are originated by the same photodiode, are generated and a WDR image signal is obtained. This technique has a distinct advantage on mitigating the problem of motion artifact in WDR imaging with high and low sensitivity signals and flexible dynamic control of the dynamic range. An experimental WDR CMOS image sensor with 280 (H) × 406 (V)-pixel array consisting of 14 sub-arrays, each of which have 20 (H) × 406 (V) pixels, was implemented and tested. For the SG on/off-time ratio of 30 and 279, the DR of 93 dB and 104 dB, respectively, was demonstrated. The effect of the proposed WDR imaging operation on the reduced motion artifact was experimentally confirmed.

show abstract

Global Shutter CMOS Image Sensor With Wide Dynamic Range

Cited by 24 publications

References 12 publications

A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers

A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers

An Improved AB<sup>2</sup>C scheme for leakage power reduction in image sensors with on-chip memory

A Wide Dynamic Range CMOS Image Sensor with a Charge Splitting Gate and Two Storage Diodes

Contact Info

Product

Resources

About