Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

Sterling, Thomas; Zima, Hans P.

doi:10.1109/sc.2002.10061

Cited by 25 publications

(14 citation statements)

References 23 publications

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“…This system includes eight DRAM PIM array chips and two FPGA chips implementing an interconnect network. Sterling and Zima [2002] studied Gilgamesh, an architecture that extends existing PIM capabilities by incorporating advanced mechanisms for virtualizing tasks and data and providing adaptive resource management for load balancing and latency tolerance. The Gilgamesh execution model is based on a middleware layer allowing explicit and dynamic control of locality and load balancing.…”

Section: Related Workmentioning

confidence: 99%

GP-SIMD Processing-in-Memory

Morad

Yavits

Ginosar

2015

ACM Trans. Archit. Code Optim.

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AMIR MORAD, LEONID YAVITS, and RAN GINOSAR, Technion GP-SIMD, a novel hybrid general-purpose SIMD computer architecture, resolves the issue of data synchronization by in-memory computing through combining data storage and massively parallel processing. GP-SIMD employs a two-dimensional access memory with modified SRAM storage cells and a bit-serial processing unit per each memory row. An analytic performance model of the GP-SIMD architecture is presented, comparing it to associative processor and to conventional SIMD architectures. Cycle-accurate simulation of four workloads supports the analytical comparison. Assuming a moderate die area, GP-SIMD architecture outperforms both the associative processor and conventional SIMD coprocessor architectures by almost an order of magnitude while consuming less power.

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Section: Related Workmentioning

confidence: 99%

GP-SIMD Processing-in-Memory

Morad

Yavits

Ginosar

2015

ACM Trans. Archit. Code Optim.

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“…The DIVA architecture incorporated a variant of the parcels message driven protocol initially devised for the HTMT architecture [14]. Parcels have continued to be used as the basis for the Gilgamesh MIND architecture [15] developed by Sterling and the Cascade architecture under development by Cray Inc.…”

Section: Related Research In the Fieldmentioning

confidence: 99%

The “MIND” scalable PIM architecture

Sterling

Brodowicz

2005

Grid Computing the New Frontier of High Performance Computing

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MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. It is a Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die. MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components. MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction processing. MIND is designed to operate either in conjunction with other conventional microprocessors or in standalone arrays of like devices. It also incorporates mechanisms for fault tolerance, real time execution, and active power management. This paper describes the major elements and operational methods of the MIND architecture.

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“…Parcels may be viewed as an outgrowth of other lightweight messaging schemes for multithreaded systems, such the MDP [9], J-Machine [26], TAM [7], and Active Messages [35]. The concept of parcels has formed the basis for several PIM designs including HTMT [32], DIVA [11], and MIND/Gilgamesh [33]. A parcel contains the following information:…”

Section: Parcelsmentioning

confidence: 99%

A low cost, multithreaded processing-in-memory system

Brockman

Thoziyoor

Kuntz

et al. 2004

Proceedings of the 3rd Workshop on Memory Performance Issues in Conjunction With the 31st International Symposium on Computer A

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This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of a commodity DRAM part, it is possible to realize a performance speedup of nearly a factor of 4 on irregular applications. This cost efficiency derives from developing a custom multithreaded processor architecture and implementation style that is well-suited for embedding in a memory. Specifically, it takes advantage of the low latency and high row bandwidth to both simplify processor design-reducing area-as well as to improve processing throughput. To support our claims of cost and performance, we have used simulation, analysis of existing chips, and also designed and fully implemented a prototype chip, PIM Lite.

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Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

Cited by 25 publications

References 23 publications

GP-SIMD Processing-in-Memory

GP-SIMD Processing-in-Memory

The “MIND” scalable PIM architecture

A low cost, multithreaded processing-in-memory system

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