GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

Galeti, Milene; Rodrigues, Michele; Martino, João Antônio; Collaert, N.; Simoen, Eddy; Claeys, Cor

doi:10.1016/j.sse.2011.11.015

Cited by 7 publications

(6 citation statements)

References 22 publications

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“…Figures 4(a the increase of barrier height by a narrower fin width [18,19]. In addition, I ON /I OFF of the ZA-11 (ZA-21) FinFET is higher than that of the Z0-11 (Z0-21) device, which is also attributed to lower I OFF in the ZA-11 (ZA-21) device as a result of the suppressed gate-induced drain leakage (GIDL).…”

Section: Resultsmentioning

confidence: 98%

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Tsai

Wang

Chen

et al. 2018

Semicond. Sci. Technol.

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The electrical characteristics of FinFETs with a crystalline ZrO 2 /Al 2 O 3 buffer layer gate stack and a crystalline ZrO 2 high-K dielectric single layer, along with different fin widths and gate lengths, are investigated. Compared with the FinFETs with a single layer of crystalline ZrO 2 high-K dielectric, the gate stack comprising the crystalline ZrO 2 /Al 2 O 3 buffer layer on FinFETs leads to the suppression of short channel effects in terms of a low drain induced barrier lowering, reduced threshold voltage roll-off, and improved subthreshold swing. The ON/OFF current ratio and gate leakage current of FinFETs are also improved by the crystalline ZrO 2 /Al 2 O 3 buffer layer gate stack. The improvement of electrical characteristics is ascribed to the reduced interface state density and gate leakage as a result of the insertion of an Al 2 O 3 buffer layer between ZrO 2 and Si. The results demonstrate that the crystalline ZrO 2 /Al 2 O 3 buffer layer structure is a promising high-K gate stack for next-generation nanoscale transistors.

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Section: Resultsmentioning

confidence: 98%

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Tsai

Wang

Chen

et al. 2018

Semicond. Sci. Technol.

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“…In addition, as can be observed in figure 3(b), the leakage current in off-state is almost a constant. It indicates that the leakage current of the non-optimized device with wide GeSi channels is dominated by trap assisted tunneling [20]. In contrast, the leakage current of the optimized device with narrow GeSi channels increases when gate voltage reduces.…”

Section: Optimized Stacked Narrow Gesi With Simentioning

confidence: 95%

Novel vertically stacked Ge_0.85Si_0.15nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhancedI_on(1.7X atV_OV=V_DS= 0.5 V) by Ge_0.85Si_0.15channels

Liu¹,

Huang²,

Lu³

et al. 2020

Semicond. Sci. Technol.

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An engineering solution is provided to improve the electrostatic behaviors of Ge-based channels gate-all-around FETs. We demonstrate the vertically stacked Ge 0.85 Si 0.15 channels above a Si channel, which has good subthreshold behaviors. The two Ge 0.85 Si 0.15 channels are tensily strained to improve I on . With optimized channel dimensions, the threshold voltage of Ge 0.85 Si 0.15 channels is more positive than the Si channel by quantum confinement. Therefore, the underneath Si channel with good electrostatic control dominates the subthreshold region. Good subthreshold slope=76 mV/dec and low drain-induced barrier lowering=36 mV/V are achieved. For on-state, the stacked high-mobility GeSi channels turn on after the Si channel to achieve I on of 13.9 μA per stack at V OV =V DS =0.5 V.

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“…The gate-induced drain leakage (GIDL) current was calculated from the difference at the gate voltage of 0 V of and the tangent on at drain bias (VDS) = 10 V [18] [19]. A grain boundary with an orientation difference of 5 degrees or more was defined as a grain boundary, and the Σ3 boundary was defined as not a grain boundary in Fig.…”

Section: Measuring Tft Characteristicsmentioning

confidence: 99%

Size Effects of Poly-Si Formed by Laser Annealing With Periodic Intensity Distribution on the TFT Characteristics

Mizutani

Hamano

Nakamura

et al. 2021

IEEE J. Electron Devices Soc.

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Currently, low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), which are characterized by high mobility of electrons, are fabricated by excimer laser annealing. High mobility in low-temperature polycrystalline silicon is achieved by controlling the grain size to approximately 300 nm. However, with future potential growth of active-matrix organic light-emitting diodes in terms of their increasing use as backlight in active matrix micro-LEDs, even higher mobility is required. One of the methods to improve mobility is to produce grains of sizes above 300 nm. However, as far as we know, there are no reports of investigating the dependence between the device characteristics and the grain size of above 300 nm. In this study, we examine the possibility of controlling the grain size above approximately 350 nm by laser annealing with an intensity distribution and investigate the grain size dependence of the TFT characteristics. We show that the grain size can be controlled approximately in the range of 1-2.5 µm, and mobility of 248±28 cm 2 V -1 s -1 is achieved at a grain size of 2.5 µm. Furthermore, we compare the device characteristics of the stepand-repeat and scan annealing and verify that the device characteristics do not deteriorate even during scan annealing. The study confirms that it is technically possible to produce LTPS with grain sizes controlled in the range of 1-2.5 µm for customizing device characteristics.

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GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

Cited by 7 publications

References 22 publications

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Novel vertically stacked Ge_0.85Si_0.15nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhancedI_on(1.7X atV_OV=V_DS= 0.5 V) by Ge_0.85Si_0.15channels

Size Effects of Poly-Si Formed by Laser Annealing With Periodic Intensity Distribution on the TFT Characteristics

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GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

Cited by 7 publications

References 22 publications

Suppression of short channel effects in FinFETs using crystalline ZrO2 high-K/Al2O3 buffer layer gate stack for low power device applications

Suppression of short channel effects in FinFETs using crystalline ZrO2 high-K/Al2O3 buffer layer gate stack for low power device applications

Novel vertically stacked Ge0.85Si0.15nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhancedIon(1.7X atVOV=VDS= 0.5 V) by Ge0.85Si0.15channels

Size Effects of Poly-Si Formed by Laser Annealing With Periodic Intensity Distribution on the TFT Characteristics

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Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Novel vertically stacked Ge_0.85Si_0.15nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhancedI_on(1.7X atV_OV=V_DS= 0.5 V) by Ge_0.85Si_0.15channels