Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Abstract

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

“…Major semiconductor manufacturers are investing enormous funds in reducing transistor size [1][2][3]. The device developed to overcome the short channel effect and the difficulty of the process inevitably caused by the size reduction of the transistor is a junctionless double gate JLDG MOSFET [4][5][6][7]. In this structure, there is no abrupt change of doping distribution between the source/drain and the channel, so it is easy to process and reduce the degradation of the subthreshold swing, threshold voltage shift, and drain induction barrier lowering (DIBL) caused by the transistor size reduction [8][9][10][11].…”

Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET

“…The existing three-dimensional structure mainly used an inversion-type MOSFET using a junction-based structure with different doping type and concentration between source/drain and channel, but recently reached the limit of the technology of forming a junction with decreasing channel length to nano unit [5][6][7][8]. The transistor developed to solve this problem is a junctionless MOSFET [9,10]. This structure is an accumulation-type MOSFET that overcomes process limitations by doping the source/drain and channel in the same type and concentration [11][12][13].…”

“…The transistor developed to solve this problem is a junctionless MOSFET [9,10]. This structure is an accumulation-type MOSFET that overcomes process limitations by doping the source/drain and channel in the same type and concentration [11][12][13]. In the case of the symmetrical junctionless MOSFETs, many studies have been conducted [14][15][16].…”

Subthreshold swing model using scale length for sub-10 nm junction-based double-gate MOSFETs

“…The increasing importance of various multi-gate MOSFETs has been recognized as the development and commercialization of sub-10 nm transistors has become a reality [1][2][3][4]. A double gate (DG) MOSFET, which is the simplest structure among multiple gate devices, has been studied as a device capable of reducing the short-channel effect [5][6][7].…”