Genetic algorithm based test scheduling and test access mechanism design for system-on-chips

Chattopadhyay, Subhrendu; Reddy, K. Sudhakar

doi:10.1109/icvd.2003.1183160

Cited by 14 publications

(14 citation statements)

References 16 publications

(28 reference statements)

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“…That is, among the different power values required by the different cores, we have to choose the maximum value of them and this is the limit up to which we can decrease P max . Addressing Problem II, a number of test access architectures and TAM optimisation methods have been proposed in literature [31][32][33][34][35].…”

Section: Problem To Be Solvedmentioning

confidence: 99%

“…If we consider that whatever be the partitions, the power requirement should not exceed certain power limit P max then the problem becomes further complex. Thus, as basically the problem of optimisation in the testing of VLSI circuits is a complex problem, several researchers tried to get the solution using GAs [32,[38][39][40].…”

Section: Amentioning

confidence: 99%

“…We have compared the results of Algorithm 2 (Fig. 5) with literature [31][32][33][34]. Table 11 shows the experimental results for different TAM widths.…”

Section: Problem IImentioning

confidence: 99%

“…A number of cores in SOCs d695, p22810, p34392 and p93791 are 10, 28, 19 and 32, respectively. For each SOC, the TAM widths chosen have seven instances 16,24,32,40,48,56 and 64. Columns 3, 4, 5 and 6 depict TSV limits in a 3D partition as reported in [31][32][33][34], while our work considering the partitions, B ≤ 4 and B ≤ 8 for Columns 7 and 8 depict the TSV limit.…”

Section: Problem IImentioning

confidence: 99%

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Approach of genetic algorithm for power‐aware testing of 3D IC

Kaibartta

Giri

Rahaman

et al. 2019

IET Computers & Digital Techniques

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The interconnect between the cores of System-on-Chip (SOC) degrades the circuit performance by contributing to circuit delay and power consumption. To reduce this problem, SOC-based three-dimensional (3D) integrated circuit (IC) technology as a promising solution where multiple layers are stacked together decreasing the length of interconnect. However, 3D IC invites some new problems including more complexity in test generation. Testing of 3D IC requires test access architecture called Test Access Mechanism (TAM) for the purpose of transport of test stimuli to the cores placed in different layers. During testing due to increasing switching activity, any circuit demands higher power consumption and it becomes more acute for 3D IC. Moreover, testing of 3D ICs has other constraints. In this study, the authors address the issue of 3D IC testing using genetic algorithm-based approach to decrease test time. At first, available TAM width is partitioned into some fixed groups and they have to find partitioning of TAM and distribution of cores among layers with a goal to decrease test time. Next, they do the same considering, variable partitions with or without certain power limits. Experimental results establish the efficacy of the authors' method.

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Section: Problem To Be Solvedmentioning

confidence: 99%

Section: Amentioning

confidence: 99%

“…We have compared the results of Algorithm 2 (Fig. 5) with literature [31][32][33][34]. Table 11 shows the experimental results for different TAM widths.…”

Section: Problem IImentioning

confidence: 99%

Section: Problem IImentioning

confidence: 99%

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Approach of genetic algorithm for power‐aware testing of 3D IC

Kaibartta

Giri

Rahaman

et al. 2019

IET Computers & Digital Techniques

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“…In that way core under test (CUT) is connected with external resources. IEEE P1500 [4] is the exactly thread to be proposed as embedded test structure.…”

Section: Quantum Algorithm Mathematical Model Designmentioning

confidence: 99%

Test scheme of SOC test with multi-constrained to reduce test time

Zhang

2009

2009 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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SOC integrates an intact system on one single chip, so that the size of chip is dwindled. However, the difficulty and complexity of system circuit testing is increased. Kinds of constraint conditions should be considered in testing cores, in order to meet the high-performance requirements of circuit system test, including the realization of parallel module test with test power and priority constrains. SOC test structural optimization is NP-hard problem, and it is hard to be solved using the common traditional arithmetic because of its complexity. While quantum search algorithm may reach to N magnitude acceleration, it is applicable to solve NP problems.In this paper, by combining quantum algorithm with encapsulation standards based on test bus and IEEE P1500 test wrapper, the policy of TAM based on test bus is analyzed. Firstly a mathematical model of SOC test scheme with test power and priority constraints is presented based on the quantum algorithm, by distributing TAM width, choosing an appropriate parameter, and using the superiority of quantum bit in solving NP problems. Next correlative test scheme algorithm is designed. Then, in the paper partial SOC circuits in ITC'02 test benchmarks are taken as experimentation objects. Compared with other similar algorithms, experimental results showed that QA has a better performance and it gets a comparatively shorter testing time.

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An Approach to the Design of Optimal Test Scheduling for System-On-Chip Based on Genetic Algorithm

Sakthivel

Narayanasamy

Innovations and Advanced Techniques in Computer and Information Sciences and Engineering

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Genetic algorithm based test scheduling and test access mechanism design for system-on-chips

Cited by 14 publications

References 16 publications

Approach of genetic algorithm for power‐aware testing of 3D IC

Approach of genetic algorithm for power‐aware testing of 3D IC

Test scheme of SOC test with multi-constrained to reduce test time

An Approach to the Design of Optimal Test Scheduling for System-On-Chip Based on Genetic Algorithm

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