Genetic algorithm based approach for low power combinational circuit testing

Abstract

With the advancement in automation, periodic testing of electronic circuits during their lifetime is becoming more and more important. For such a circuit, it is thus very much necessary to reduce the power requirement during the testing phase also. This paper presents a Genetic Algorithm based formulation to solve the problem of generating a test pattern set such that it has high fault coverage and low power consumption. Exhaustive experimentation done on ISCAS85 combinational benchmark suite has shown that the this tool results in upto 78% reduction in transition activity over the original test set generated by ATPGs like ATALANTA [1].

Dynamic Power Minimization During Combinational Circuit Testing as a Traveling Salesman Problem

“…A genetic algorithm-based approach for combinational circuit testing was proposed by Chattopadhyay and Choudhary [2]. While the actual vector reordering was done using Prim's Algorithm, the chromosomes of Chattopadhyay's genetic algorithm were used to represent subsets of the original test set.…”

“…Using a number of operators, they were able to find a remarkably low value for switching activity at the cost of reduced fault coverage. More specifically, a 3-4% decrease in fault coverage has been demonstrated to yield a 70% reduction in switching activity [2].…”

“…Prior experimental results [1], [2], [3], [4] show that test vector ordering in the context of combinational and sequential circuit testing can reduce power dissipation by an order of magnitude compared to the original unordered test set generated by a traditional automatic test pattern generator (ATPG). The test set re-ordering problem can be reduced to the well-known traveling salesman problem (TSP), where the individual test vectors are the cities and the Hamming distance between any two test vectors is the distance between those two cities [1], [15].…”

“…Chattopadhyay and Choudhary have shown [2] that by sacrificing a small amount of fault coverage it is possible to select a representative subset of test vectors generated by an ATPG and achieve a further decrease in power dissipation. Fault coverage is defined as the number of faults detected divided by the total number of faults under a given fault model [20], [21].…”

“…Deb's NSGA-II [13] is used to construct a Pareto-front of multiple subsets from the original generated test vectors. We argue that generating a Pareto-front provides more flexibility in selecting a proper solution for some particular application than generating a single solution using a fixed weighted objective function that combines fault coverage and power dissipation, as observed in [2].…”