Dynamic Power Minimization During Combinational Circuit Testing as a Traveling Salesman Problem

Abstract

Abstract-Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume significant dynamic power during testing because of enhanced switching activity in the internal nodes. Our work focuses on the fact that power minimization is a Traveling Salesman Problem (TSP). We explore application of local search and genetic algorithms to test set reordering and perform a quantitative comparison to previously used deterministic techniques. We also consider reduction of the original test set as a dual-objective optimization problem, where switching activity and fault coverage are the two objective functions.

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

“…This is because in MT fill the X-bits are filled on the basis of specified bit on the same bit position in the previous test vector. Table 9 shows the comparison of ASA of the proposed work with Sokolov et al (2005) and Girard et al (1998). ASA is observed to be reduced for most of the benchmark circuits as compared to the results mentioned in Sokolov et al (2005) and Girard et al (1998).…”

“…Table 9 shows the comparison of ASA of the proposed work with Sokolov et al (2005) and Girard et al (1998). ASA is observed to be reduced for most of the benchmark circuits as compared to the results mentioned in Sokolov et al (2005) and Girard et al (1998). Table 9 Comparison of ASA Circuit MT-fill Sokolov et al (2005) Girard et al (1998 …”

Low Power Testing of VLSI Circuits Using Test Vector Reordering

“…The results are tabulated in Table IV and Table V for average power and peak power respectively. The results are also compared with unordered test sets and switching activity based reordered test set [9]- [11].…”

“…To overcome the difficulty, the actual switching activity is considered for reordering the test vectors. Other reordering algorithms based on hamming distance [8] and internal switching activity [9]- [11] also found in literatures.…”

WTM based reordering of combine test vector & output response using Dijkstra algorithm for scan power reduction

“…The second category consists of ordering techniques [5,6,4,8], in which the switching activity is reduced by modifying the order in which test vectors of a given test sequence are applied to the CUT. The paper [3] discussed about two methods used for reordering of test vectors in order to reduce the dynamic power dissipation during testing of combinational circuits. Two search methods 2-opt heuristic and a genetic algorithm based approach has applied and results obtained for combinational circuits.…”